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| this is information on a product in full production. march 2016 docid027101 rev 3 1/136 stm32l071x8 stm32l071xb stm32l071xz access line ultra-low-power 32-bit mcu arm ? -based cortex ? -m0+, up to 192kb flash, 20kb sram, 6kb eeprom, adc datasheet - production data features ? ultra-low-power platform ? 1.65 v to 3.6 v power supply ? - 40 to 125 c temperature range ? 0.29 a standby mode (3 wakeup pins) ? 0.43 a stop mode (16 wakeup lines) ? 0.86 a stop mode + rtc + 20 kb ram retention ? down to 93 a/mhz in run mode ? 5 s wakeup time (from flash memory) ? 41 a 12-bit adc conversion at 10 ksps ? core: arm ? 32-bit cortex ? -m0+ with mpu ? from 32 khz up to 32 mhz max. ? 0.95 dmips/mhz ? reset and supply management ? ultra-safe, low-power bor (brownout reset) with 5 selectable thresholds ? ultra-low-power por/pdr ? programmable voltage detector (pvd) ? clock sources ? 1 to 25 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? high speed internal 16 mhz factory-trimmed rc (+/- 1%) ? internal low-power 37 khz rc ? internal multispeed low-power 65 khz to 4.2 mhz rc ? pll for cpu clock ? pre-programmed bootloader ? usart, i2c, spi supported ? development support ? serial wire debug supported ? up to 84 fast i/os (78 i/os 5v tolerant) ? memories ? up to 192 kb flash memory with ecc(2 banks with read-while-write capability) ?20 kb ram ? 6 kb of data eeprom with ecc ? 20-byte backup register ? sector protection against r/w operation ? rich analog peripherals ? 12-bit adc 1.14 msps up to 16 channels (down to 1.65 v) ? 2x ultra-low-power comparators (window mode and wake up capability, down to 1.65 v) ? 7-channel dma controller, supporting adc, spi, i2c, usart, timers ? 10x peripheral communication interfaces ? 4 x usart ( 2 with iso 7816, irda), 1x uart (low power) ? up to 6x spi 16 mbits/s ? 3 x i2c ( 2 with smbus/pmbus) ? 11x timers: 2x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x systick, 1x rtc, 2x 16-bit basic, and 2x watchdogs (independent/window) ? crc calculation unit, 96-bit unique id ? all packages are ecopack ? 2 table 1. device summary reference part number stm32l071x8 stm32l071v8, stm32l071k8, stm32l071c8 stm32l071xb stm32l071vb, stm32l071rb, stm32l071cb, stm32l071kb stm32l071xz stm32l071vz, stm32l071rz, stm32l071cz, STM32L071KZ ) % * $ lqfp32 7x7 mm lqfp48 7x7 mm lqfp64 10x10 mm lqfp100 14x14 mm wlcsp49 (3.294x3.258 mm) ufbga64 tfbga64 5x5mm ufbga100 7x7 mm ) % * $ ufqfpn32 5x5 mm www.st.com
contents stm32l071xx 2/136 docid027101 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 arm? cortex?-m0+ core with mpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12.1 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14.1 general-purpose timers (tim2, tim3, tim21 and tim22) . . . . . . . . . . . 28 3.14.2 low-power timer (lptim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.3 basic timer (tim6, tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.4 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.5 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.6 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 docid027101 rev 3 3/136 stm32l071xx contents 4 3.15.1 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.2 universal synchronous/asynchronous receiver transmitter (usart) . . 31 3.15.3 low-power universal asynchronous receiver transmitter (lpuart) . . . 31 3.15.4 serial peripheral interface (spi)/inter-integrated sound (i2s) . . . . . . . . 32 3.16 cyclic redundancy check (crc) calculation unit . . . . . . . . . . . . . . . . . . . 32 3.17 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 embedded reset and power control bloc k characteristics . . . . . . . . . . . 59 6.3.3 embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3.5 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.15 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 contents stm32l071xx 4/136 docid027101 rev 3 6.3.16 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.17 comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.19 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.1 lqfp100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 7.2 ufbga100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 7.3 lqfp64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 7.4 tfbga64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 7.5 wlcsp49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.6 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.7 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.8 ufqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.9 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.9.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 docid027101 rev 3 5/136 stm32l071xx list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. ultra-low-power stm32l071xx device features and peripheral counts . . . . . . . . . . . . . . . 11 table 3. functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15 table 4. cpu frequency range depending on dynamic voltag e scaling . . . . . . . . . . . . . . . . . . . . . . 16 table 5. functionalities depending on the working mode ? (from run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. stm32l0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11. stm32l071xx i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 14. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. stm32l071xxx pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. alternate functions port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 17. alternate functions port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 18. alternate functions port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 19. alternate functions port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 20. alternate functions port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21. alternate functions port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 22. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 24. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 26. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 27. embedded internal reference voltage calibration valu es . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 28. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 table 29. current consumption in run mode, code with data processing running from ? flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 30. current consumption in run mode vs code type, ? code with data processing running from flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 31. current consumption in run mode, code wit h data processing running from ram . . . . . . 64 table 32. current consumption in run mode vs code type, ? code with data processing running from ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 33. current consumption in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 34. current consumption in low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 35. current consumption in low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 36. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . . 69 table 38. average current consumption during wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 39. peripheral current consumption in run or sleep mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. peripheral current consumption in stop and stan dby mode . . . . . . . . . . . . . . . . . . . . . . . 73 table 41. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 42. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 43. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 44. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 list of tables stm32l071xx 6/136 docid027101 rev 3 table 45. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 46. 16 mhz hsi16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 table 47. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 48. msi oscillator ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 49. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 50. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 51. flash memory and dat a eeprom characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 52. flash memory and data eeprom endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 83 table 53. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 54. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 55. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 56. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 57. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 58. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 59. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 60. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 61. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 62. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 63. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 64. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 65. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 table 66. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 67. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 68. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 69. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 70. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 71. usart/lpuart characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 72. spi characteristics in voltage range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 table 73. spi characteristics in voltage range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 table 74. spi characteristics in voltage range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 table 75. i2s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 76. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package ? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 77. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array ? package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 78. ufbga100 recommended pcb design rules (0.5 mm pitch bga) . . . . . . . . . . . . . . . . . 112 table 79. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat ? package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 80. tfbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ? grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 81. tfbga64 recommended pcb design rules (0.5 mm pitch bga). . . . . . . . . . . . . . . . . . . 117 table 82. wlcsp49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale ? package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 83. wlcsp49 recommended pcb design rules (0.4 mm pi tch) . . . . . . . . . . . . . . . . . . . . . . 121 table 84. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 123 table 85. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 126 table 86. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat ? package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 87. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 88. stm32l071xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 89. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 docid027101 rev 3 7/136 stm32l071xx list of figures 8 list of figures figure 1. stm32l071xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 3. stm32l071xx lqfp100 pinout - 14 x 14 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4. stm32l071xx ufbga100 ballout - 7x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 5. stm32l071xx lqfp64 pinout - 10 x 10 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6. stm32l071xx tfbga64 ballout - 5x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 7. stm32l071xx wlcsp49 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 8. stm32l071xx lqfp48 pinout - 7 x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9. stm32l071xx lqfp32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figure 10. stm32l071xx ufqfpn32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 11. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 12. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 13. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 14. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 15. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 16. idd vs vdd, at ta= 25/55/85 /105 c, run mode, code running from ? flash memory, range 2, hse, 1ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 17. idd vs vdd, at ta= 25/55/85 /105 c, run mode, code running from ? flash memory, range 2, hsi16, 1ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 18. idd vs vdd, at ta= 25 c, low-power run mode, code running ? from ram, range 3, msi (range 0) at 64 khz, 0 ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 19. idd vs vdd, at ta= 25/55/ 85/105/125 c, stop mode with rtc enabled ? and running on lse low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 20. idd vs vdd, at ta= 25/55/85/ 105/125 c, stop mode with rtc disabled, ? all clocks off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 21. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 22. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 23. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 24. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 25. hsi16 minimum and maximum value versus temperat ure . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 26. vih/vil versus vdd (cmos i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 figure 27. vih/vil versus vdd (ttl i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 28. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 29. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 30. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 31. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 32. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 97 figure 33. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 98 figure 34. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 35. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 36. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 37. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 38. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 39. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 108 figure 40. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat ? recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 41. lqfp100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 42. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball ? list of figures stm32l071xx 8/136 docid027101 rev 3 grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 43. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball ? grid array package recommended footpr int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 44. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 113 figure 45. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 114 figure 46. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 47. tfbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball ? grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 48. tfbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball ? ,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 49. tfbga64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 50. wlcsp49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale ? package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 51. wlcsp49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale ? recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 52. wlcsp49 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 53. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 122 figure 54. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 124 figure 55. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 56. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 125 figure 57. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 126 figure 58. lqfp32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 59. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat ? package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 60. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat ? recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 61. ufqfpn32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 62. thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 docid027101 rev 3 9/136 stm32l071xx introduction 32 1 introduction the ultra-low-power stm32l071xx are offered in 9 different package types from 32 pins to 100 pins. depending on the device chosen, diff erent sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. these features make the ultra-low-power stm32l071xx microcontrollers suitable for a wide range of applications: ? gas/water meters and industrial sensors ? healthcare and fitness equipment ? remote control and user interface ? pc peripherals, gaming, gps equipment ? alarm system, wired and wireless sensors, video intercom this stm32l071xx datasheet should be read in conjunction with the stm32l0x1xx reference manual (rm0377) . for information on the arm ? cortex ? -m0+ core please refer to the cortex ? -m0+ technical reference manual, available from the www.arm.com website. figure 1 shows the general block diagram of the device family. description stm32l071xx 10/136 docid027101 rev 3 2 description the access line ultra-low-power stm32l071xx microcontrollers incorporate the high- performance arm ? cortex ? -m0+ 32-bit risc core operating at a 32 mhz frequency, a memory protection unit (mpu), hi gh-speed embedded memories (up to 192 kbytes of flash program memory, 6 kbytes of data eeprom and 20 kbytes of ram) plus an extensive range of enhanced i/os and peripherals. the stm32l071xx devices provide high power efficiency for a wide range of performance. it is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes. the stm32l071xx devices offer several analog features, one 12-bit adc with hardware oversampling, two ultra-low-power comparators, several timers, one low-power timer (lptim), four general-purpose 16-bit timers and two basic timer, one rtc and one systick which can be used as timebases. they al so feature two watchd ogs, one watchdog with independent clock and window capability and one window wa tchdog based on bus clock. moreover, the stm32l071xx devices embed standard and advanced communication interfaces: up to three i2cs, two spis, one i2s, four usarts, a low-power uart (lpuart), . the stm32l071xx also include a real-time clock and a set of backup registers that remain powered in standby mode. the ultra-low-power stm32l071xx devices operat e from a 1.8 to 3.6 v power supply (down to 1.65 v at power down) with bor and from a 1.65 to 3.6 v power supply without bor option. they are available in the -40 to +125 c temperature range. a comprehensive set of power-saving modes allows the design of low-power applications. docid027101 rev 3 11/136 stm32l071xx description 32 2.1 device overview table 2. ultra-low-power stm32l071xx de vice features and peripheral counts peripheral stm32l 071k8 stm32l 071c8 stm32l 071v8 stm32l 071kb stm32l 071cb stm32l 071vb stm32l 071rb stm32l 071kz stm32l 071cz stm32l 071vz stm32l 071rz flash (kbytes) 64 kbytes 128 kbytes 192 kbytes data eeprom (kbytes) 3 kbytes 6 kbytes ram (kbytes) 20 kbytes timers general- purpose 4 basic 2 lptimer 1 rtc/systick/iwdg /wwdg 1/1/1/1 com. interfaces spi/i2s 4(3) (1) /0 6(4) (2) /1 4(3) (1) /0 6(4) (2) /1 4(3) (1) /0 6(4) (2) /1 i 2 c 23 2 3 2 3 usart 34 3 4 3 4 lpuart 1 gpios 23 37 84 25 (3) 40 (4) 84 51 (5) 25 (3) 40 (4) 84 51 (5) clocks: hse/lse/hsi/msi/lsi 1/1/1/1/1 12-bit synchronized adc ? number of channels 1 10 1 13 1 16 1 10 1 13 (4) 1 16 1 16 (5) 1 10 1 13 (4) 1 16 1 16 (5) comparators 2 max. cpu frequency 32 mhz operating voltage 1.8 v to 3.6 v (down to 1.65 v at power-down) with bor option 1.65 to 3.6 v without bor option operating temperatures ambient temperature: ?40 to +125 c junction temperature: ?40 to +130 c packages ufqfpn 32 lqfp48 lqfp/ ufbga 100 ufqfpn/ lqfp32 lqfp48, wlcsp49 lqfp/ ufbga 100 lqfp/ tfbga 64 ufqfpn/ lqfp32 lqfp48, wlcsp49 lqfp/ ufbga 100 lqfp/ tfbga 64 1. 3 spi interfaces are usarts operating in spi master mode. 2. 4 spi interfaces are usarts operating in spi master mode. 3. ufqfpn32 has 2 gpios less than lqfp32. 4. lqfp48 has three gpios less than wlcsp49. 5. tfbga64 has one gpio, one adc input less than lqfp64. description stm32l071xx 12/136 docid027101 rev 3 figure 1. stm32l071xx block diagram & 2 5 7 ( ; 0 & 3 8 ) p d [ 0 + ] 6 : ' 0 3 8 1 9 , & * 3 , 2 3 2 5 7 $ * 3 , 2 3 2 5 7 % 7 h p s v h q v r u 5 ( 6 ( 7 & / . ) / $ 6 + ( ( 3 5 2 0 % 2 2 7 5 $ 0 ' 0 $ $ + % ) p d [ 0 + ] & 5 & % 5 , ' * ( $ 3 % ) , 5 ( : $ / / ' % * ( ; 7 , $ ' & 6 3 , 8 6 $ 5 7 7 , 0 & 2 0 3 / 6 ( 7 , 0 % 5 , ' * ( $ 3 % 7 , 0 5 $ 0 . , & , & 8 6 $ 5 7 / 3 8 $ 5 7 6 3 , , 6 7 , 0 , : ' * 5 7 & : : ' * / 3 7 , 0 % & . 3 5 ( * + 6 ( + 6 , 0 3 / / 0 6 , / 6 , 3 0 8 5 ( * 8 / $ 7 2 5 9 ' ' 9 ' ' $ 9 5 ( ) b 2 8 7 1 5 6 7 3 9 ' b , 1 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 : . 8 3 [ 3 $ > @ 3 % > @ $ , 1 [ 0 , 6 2 0 2 6 , 6 & . 1 6 6 5 ; 7 ; 5 7 6 & 7 6 & . f k f k , 1 3 , 1 0 2 8 7 , 1 , 1 ( 7 5 2 8 7 6 & / 6 ' $ 6 0 % $ 6 & / 6 ' $ 5 ; 7 ; 5 7 6 & 7 6 & . 5 ; 7 ; 5 7 6 & 7 6 0 , 6 2 0 & . 0 2 6 , 6 ' 6 & . & . 1 6 6 : 6 f k 6 : ' 0 6 y 9 & 2 0 3 , 1 3 , 1 0 2 8 7 7 , 0 , & 6 & / 6 ' $ 6 0 % $ 8 6 $ 5 7 5 ; 7 ; 5 7 6 & 7 6 & . 8 6 $ 5 7 5 ; 7 ; 5 7 6 & 7 6 & . 7 , 0 f k docid027101 rev 3 13/136 stm32l071xx description 32 2.2 ultra-low-power device continuum the ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to arm ? cortex ? -m4, including arm ? cortex ? -m3 and arm ? cortex ? -m0+. the stm32lx series are the best choice to answer your needs in terms of ultra-low-power features. the stm32 ultra-low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fitness and healthcare application. several built-in features like lcd drivers, dual-bank memory, low-power run mode, operational amplifiers, 128-bit aes, dac, crystal-less usb and many other definitely help you building a highly cost optimized application by reducing bom cost. stmicroelectronics, as a reliable and long-term manufacturer, ensures as much as possible pin-to -pin compatibility between all stm8lx and stm32lx on one hand, and between all stm32lx and stm32fx on the other hand. thanks to this un precedented scalability, your legacy applicat ion can be upgraded to respond to the latest market feature and efficiency requirements. functional overview stm32l071xx 14/136 docid027101 rev 3 3 functional overview 3.1 low-power modes the ultra-low-power stm32l071xx support dyna mic voltage scaling to optimize its power consumption in run mode. the voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system?s maximum operating frequency and the external voltage supply. there are three power consumption ranges: ? range 1 (v dd range limited to 1.71-3.6 v), with the cpu running at up to 32 mhz ? range 2 (full v dd range), with a maximum cpu frequency of 16 mhz ? range 3 (full v dd range), with a maximum cpu frequency limited to 4.2 mhz seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. sleep mode power consumption at 16 mhz is about 1 ma with all peripherals off. ? low-power run mode this mode is achieved with t he multispeed in ternal (msi) rc oscilla tor set to the low- speed clock (max 131 khz), execution from sram or flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. in low- power run mode, the clock frequency and the number of enabled peripherals are both limited. ? low-power sleep mode this mode is achieved by entering sleep mode with the internal voltage regulator in low-power mode to minimize the regulator?s operating current. in low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 khz. when wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. stop mode with rtc the stop mode achieves the lowest powe r consumption while retaining the ram and register contents and real time clock. all clocks in the v core domain are stopped, the pll, msi rc, hse crystal and hsi rc oscillato rs are disabled. the lse or lsi is still running. the voltage regulator is in the low-power mode. some peripherals featuring wakeup capability can enable the hsi rc during stop mode to detect their wakeup condition. the device can be woken up from stop mode by any of the exti line, in 3.5 s, the processor can serve the interrupt or resume the code. the exti line source can be any gpio. it can be the pvd output, the comp arator 1 event or comparator 2 event (if internal reference voltage is on), it c an be the rtc alarm/tamper/timestamp/wakeup events, the usart/i2c/lpuart/lptimer wakeup events. docid027101 rev 3 15/136 stm32l071xx functional overview 32 ? stop mode without rtc the stop mode achieves the lowest powe r consumption while retaining the ram and register contents. all clocks are stopped, the pll, msi rc, hsi and lsi rc, hse and lse crystal oscillators are disabled. some peripherals featuring wakeup capability can enable the hsi rc during stop mode to detect their wakeup condition. the voltage regulator is in the low-power mode. the device can be woken up from stop mode by any of the exti line, in 3.5 s, the processor can serve the interrupt or resume the code. the exti line source can be any gpio. it can be the pvd output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). it can also be wakened by the usart/i2 c/lpuart/lptimer wakeup events. ? standby mode with rtc the standby mode is used to achieve the lowest power consumption and real time clock. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hse crystal and hsi rc oscillators are also switched off. the lse or lsi is still running. after entering standby mode, the ram and register contents are lost except fo r registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr register). the device exits standby mode in 60 s when an external reset (nrst pin), an iwdg reset, a rising edge on one of the three wkup pins, rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup event occurs. ? standby mode without rtc the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire v core domain is powered off. the pll, msi rc, hsi and lsi rc, hse and lse cr ystal oscillators are also switched off. after entering standby mode, the ram and register contents are lost except for registers in the standby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr register). the device exits standby mode in 60 s when an external reset (nrst pin) or a rising edge on one of the three wkup pin occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped automatically by entering stop or standby mode. table 3. functionalities depending on the operating power supply range operating power supply range functionalities depending on the operating power supply range adc operation dynamic voltage scaling range i/o operation v dd = 1.65 to 1.71 v adc only, conversion time up to 570 ksps range 2 or range 3 degraded speed performance v dd = 1.71 to 1.8 v (1) adc only, conversion time up to 1.14 msps range 1, range 2 or range 3 degraded speed performance v dd = 1.8 to 2.0 v (1) conversion time up to 1.14 msps range1, range 2 or range 3 degraded speed performance functional overview stm32l071xx 16/136 docid027101 rev 3 v dd = 2.0 to 2.4 v conversion time up to 1.14 msps range 1, range 2 or range 3 full speed operation v dd = 2.4 to 3.6 v conversion time up to 1.14 msps range 1, range 2 or range 3 full speed operation 1. cpu frequency changes from initial to final must respec t "fcpu initial <4*fcpu final". it must also respect 5 s delay between two changes. for example to switch fr om 4.2 mhz to 32 mhz, you can switch from 4.2 mhz to 16 mhz, wait 5 s, then switch from 16 mhz to 32 mhz. table 4. cpu frequency range de pending on dynamic voltage scaling cpu frequency range dynamic voltage scaling range 16 mhz to 32 mhz (1ws) 32 khz to 16 mhz (0ws) range 1 8 mhz to 16 mhz (1ws) 32 khz to 8 mhz (0ws) range 2 32 khz to 4.2 mhz (0ws) range 3 table 3. functionalities depending on the operating power supply range (continued) operating power supply range functionalities depending on the operating power supply range adc operation dynamic voltage scaling range i/o operation table 5. functionalities depending on the working mode (from run/active down to standby) (1)(2) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability cpu y -- y -- -- -- flash memory o o o o -- -- ram y y y y y -- backup registers y y y y y y eeprom o o o o -- -- brown-out reset (bor) oooooooo dma o o o o -- -- programmable voltage detector (pvd) oooooo- power-on/down reset (por/pdr) yyyyyyyy high speed internal (hsi) oo---- (3) -- docid027101 rev 3 17/136 stm32l071xx functional overview 32 high speed external (hse) oooo-- -- low speed internal (lsi) ooooo o low speed external (lse) ooooo o multi-speed internal (msi) ooyy-- -- inter-connect controller yyyyy -- rtc o o o o o o o rtc tamper o o o o o o o o auto wakeup (awu) oooooooo usart o o o o o (4) o-- lpuart o o o o o (4) o-- spi o o o o -- -- i2c o o o o o (5) o-- adc o o -- -- -- -- temperature sensor ooooo -- comparators o o o o o o -- 16-bit timers o o o o -- -- lptimer o o o o o o iwdg o o o o o o o o wwdg o o o o -- -- systick timer o o o o -- gpios o o o o o o 2 pins wakeup time to run mode 0 s 0.36 s 3 s 32 s 3.5 s 50 s table 5. functionalities depending on the working mode (from run/active down to standby) (continued) (1)(2) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability functional overview stm32l071xx 18/136 docid027101 rev 3 3.2 interconnect matrix several peripherals are directly interconnec ted. this allows autonomous communication between peripherals, thus saving cpu resources and power consumption. in addition, these hardware connections allow fast and predictable latency. depending on peripherals, these interconnect ions can operate in run, sleep, low-power run, low-power sleep and stop modes. consumption v dd =1.8 to 3.6 v (typ) down to 140 a/mhz (from flash memory) down to 37 a/mhz (from flash memory) down to 8 a down to 4.5 a 0.4 a (no rtc) v dd =1.8 v 0.28 a (no rtc) v dd =1.8 v 0.8 a (with rtc) v dd =1.8 v 0.65 a (with rtc) v dd =1.8 v 0.4 a (no rtc) v dd =3.0 v 0.29 a (no rtc) v dd =3.0 v 1 a (with rtc) v dd =3.0 v 0.85 a (with rtc) v dd =3.0 v 1. legend: ? ?y? = yes (enable). ? ?o? = optional can be enabled/disabled by software) ? ?-? = not available 2. the consumption values given in this ta ble are preliminary data given for indicati on. they are subject to slight changes. 3. some peripherals with wakeup from stop capability can reques t hsi to be enabled. in this case, hsi is woken up by the peripheral, and only feeds the peripheral which requested it. hsi is automatically put off when the peripheral does not need it anymore. 4. uart and lpuart reception is functional in stop mode. it generates a wakeup interrupt on start. to generate a wakeup on address match or received frame event, the lpuart can run on lse clock while the uart has to wake up or keep running the hsi clock. 5. i2c address detection is functional in stop mode. it generates a wakeup interrupt in case of address match. it will wake up the hsi during reception. table 5. functionalities depending on the working mode (from run/active down to standby) (continued) (1)(2) ips run/active sleep low- power run low- power sleep stop standby wakeup capability wakeup capability table 6. stm32l0xx peripherals interconnect matrix interconnect source interconnect destination interconnect action run sleep low- power run low- power sleep stop compx tim2,tim21, tim22 timer input channel, trigger from analog signals comparison yy y y - lptim timer input channel, trigger from analog signals comparison yy y y y timx timx timer triggered by other timer yy y y - docid027101 rev 3 19/136 stm32l071xx functional overview 32 3.3 arm ? cortex ? -m0+ core with mpu the cortex-m0+ processor is an entry-level 32-bit arm cortex processor designed for a broad range of embedded applications. it offers significant benefits to developers, including: ? a simple architecture that is easy to learn and program ? ultra-low power, energy-efficient operation ? excellent code density ? deterministic, high-performance interrupt handling ? upward compatibility with co rtex-m processor family ? platform security robustness, with in tegrated memory protection unit (mpu). the cortex-m0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline von neumann arch itecture. the processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier. the cortex-m0+ processor provides the except ional performance expected of a modern 32- bit architecture, with a higher code density t han other 8-bit and 16-bit microcontrollers. owing to its embedded arm core, the stm32l071xx are compatible with all arm tools and software. rtc tim21 timer triggered by auto wake-up yy y y - lptim timer triggered by rtc event yy y y y all clock source timx clock source used as input channel for rc measurement and trimming yy y y - gpio timx timer input channel and trigger yy y y - lptim timer input channel and trigger yy y y y adc conversion trigger y y y y - table 6. stm32l0xx peripherals interconnect matrix (continued) interconnect source interconnect destination interconnect action run sleep low- power run low- power sleep stop functional overview stm32l071xx 20/136 docid027101 rev 3 nested vectored interrupt controller (nvic) the ultra-low-power stm32l071xx embed a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels. the cortex-m0+ processor closely integrates a configurable nested vectored interrupt controller (nvic), to deliver industry-leading interrupt performance. the nvic: ? includes a non-mask able interrupt (nmi) ? provides zero jitte r interrupt option ? provides four interr upt priority levels the tight integration of the processor core and nvic provides fast execution of interrupt service routines (isrs), dramatically reducing the interrupt latency. this is achieved through the hardware stacking of registers, and the abilit y to abandon and restart load- multiple and store-multiple operations. interrupt handlers do not require any assembler wrapper code, removing any code overhead from the isrs. tail-chaining optimization also significantly reduces the overhead when switching from one isr to another. to optimize low-power designs, the nvic int egrates with the sleep modes, that include a deep sleep function that enables the entire device to enter rapidly stop or standby mode. this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.4 reset and supply management 3.4.1 power supply schemes ? v dd = 1.65 to 3.6 v: external power supply fo r i/os and the internal regulator. provided externally through v dd pins. ? v ssa , v dda = 1.65 to 3.6 v: external analog power supplies for adc reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. 3.4.2 power supply supervisor the devices have an integrated zeropower power-on reset (por)/power-down reset (pdr) that can be coupled with a brownout reset (bor) circuitry. two versions are available: ? the version with bor activated at power-on operates between 1.8 v and 3.6 v. ? the other version without bor oper ates between 1.65 v and 3.6 v. after the v dd threshold is reached (1.65 v or 1.8 v depending on the bor which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the bor permanently: in this case, the vdd min value becomes 1.65 v (whatever the version, bo r active or not, at power-on). when bor is active at power- on, it ensures proper operation starting from 1.8 v whatever the power ramp-up phase before it reaches 1.8 v. when bor is not active at power-up, the power ramp-up should guarantee that 1.65 v is reached on v dd at least 1 ms after it exits the por area. five bor thresholds are available through opti on bytes, starting from 1.8 v to 3 v. to reduce the power consumption in stop mode, it is possible to automatically switch off the docid027101 rev 3 21/136 stm32l071xx functional overview 32 internal reference voltage (v refint ) in stop mode. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: the start-up time at power-on is typically 3.3 ms when bor is active at power-up, the start- up time at power-on can be decreased down to 1 ms typically for devices with bor inactive at power-up. the devices feature an embedded programmable voltage detector (pvd) that monitors the v dd/vdda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd/vdda drops below the v pvd threshold and/or when v dd/vdda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.4.3 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. ? mr is used in run mode (nominal regulation) ? lpr is used in the low-power run, low-power sleep and stop modes ? power down is used in standby mode. the regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and ram are lost except for the st andby circuitry (wakeup logic, iwdg, rtc, lsi, lse crystal 32 khz oscillator, rcc_csr). 3.5 clock management the clock controller distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. it features: ? clock prescaler to get the best trade-off between speed a nd current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source three different clock sources can be used to drive the master clock sysclk: ? 1-25 mhz high-speed external crystal (hse), that can supply a pll ? 16 mhz high-speed internal rc oscillator (h si), trimmable by software, that can supply a pllmultispeed internal rc oscilla tor (msi), trimmable by software, able to generate 7 frequencies (65 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.1 mhz, 4.2 mhz). when a 32.768 khz clock so urce is available in the system (lse), the msi frequency can be trimmed by so ftware down to a 0.5% accuracy. ? auxiliary clock source two ultra-low-power clock sources that c an be used to drive the real-time clock: functional overview stm32l071xx 22/136 docid027101 rev 3 ? 32.768 khz low-speed external crystal (lse) ? 37 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock can be measured using the high-speed internal rc oscillator for greater precision. ? rtc clock source the lsi, lse or hse sources can be chosen to clock the rtc, whatever the system clock. ? startup clock after reset, the microcontroller restarts by default with an internal 2.1 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css) this feature can be enabled by software. if an hse clock failure occurs, the master clock is automatically switched to hsi and a software interrupt is generated if enabled. another clock security system can be enabled, in case of failure of the lse it provides an interrupt or wakeup event which is generated if enabled. ? clock-out capability (mco: microcontroller clock output) it outputs one of the internal clocks for external use by the application. several prescalers allow the configuration of the ahb fr equency, each apb (apb1 and apb2) domains. the maximum frequency of the ahb and the apb domains is 32 mhz. see figure 2 for details on the clock tree. docid027101 rev 3 23/136 stm32l071xx functional overview 32 figure 2. clock tree 0 6 y 9 / h j h q g + 6 ( + l j k v s h h g h [ w h u q d o f o r f n v l j q d o + 6 , + l j k v s h h g l q w h u q d o f o r f n v l j q d o / 6 , / r z v s h h g l q w h u q d o f o r f n v l j q d o / 6 ( / r z v s h h g h [ w h u q d o f o r f n v l j q d o 0 6 , 0 x o w l v s h h g l q w h u q d o f o r f n v l j q d o : d w f k g r j / 6 / 6 , 5 & / 6 ( 2 6 & 5 7 & / 6 , w h p s r # 9 + 6 , 5 & / h y h o v k l i w h u v + 6 ( 2 6 & / h y h o v k l i w h u v / 6 8 0 + ] & o r f n ' h w h f w r u / 6 ' / 6 ( w h p s r 0 6 , 5 & / h y h o v k l i w h u v / h y h o v k l i w h u v 3 / / ; $ 3 % 3 5 ( 6 & $ + % 3 5 ( 6 & ? & o r f n 6 r x u f h & r q w u r o # 9 # 9 # 9 # 9 # 9 # 9 # 9 # 9 , & & / . / 3 8 $ 5 7 8 $ 5 7 & / . / 3 7 , 0 & / . / 6 ( + 6 , 6 < 6 & / . 3 & / . / 6 , 3 h u l s k h u d o f o r f n h q d e o h 3 & / . w r $ 3 % s h u l s k h u d o v q r w v o h h s r u g h h s v o h h s q r w v o h h s r u g h h s v o h h s q r w g h h s v o h h s q r w g h h s v o h h s + & / . 6 \ v 7 l f n 7 l p h u & . b 3 : 5 ) & / . 3 / / & / . + 6 ( + 6 , 0 6 , / 6 ( / 6 , + 6 ( s u h v h q w r u q r w # 9 # 9 ' ' & 2 5 ( f n b u f k v + 6 , 0 6 , 0 + ] f n b s o o l q ( q d e o h : d w f k g r j 5 7 & h q d e o h $ ' & h q d e o h $ ' & & / . / 6 8 / 6 ' / 6 ' 0 & 2 0 & 2 6 ( / 3 / / 6 5 & 5 7 & 6 ( / 6 \ v w h p & o r f n 0 + ] p d [ , i $ 3 % s u h v f [ h o v h [ w r 7 , 0 [ 3 h u l s k h u d o f o r f n h q d e o h 3 h u l s k h u d o f o r f n h q d e o h 3 h u l s k h u d o f o r f n h q d e o h $ 3 % 3 5 ( 6 & 3 h u l s k h u d o f o r f n h q d e o h 3 & / . w r $ 3 % s h u l s k h u d o v 0 + ] p d [ , i $ 3 % s u h v f [ h o v h [ w r 7 , 0 [ 3 h u l s k h u d o f o r f n h q d e o h functional overview stm32l071xx 24/136 docid027101 rev 3 3.6 low-power real-time cl ock and backup registers the real time clock (rtc) and the 5 backup registers are supplied in all modes including standby mode. the backup registers are five 32-b it registers used to store 20 bytes of user application data. they are not reset by a system reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month ? two programmable alarms with wake up from stop and stan dby mode capability ? periodic wakeup from stop and standby with programmable resolution and period ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy ? 2 anti-tamper detection pins with programma ble filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 37 khz) ? the high-speed external clock 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated alternate function regi sters. all gpios are high current capable. each gpio output, speed can be slowed (40 mh z, 10 mhz, 2 mhz, 400 khz). the alternate function configuration of i/os can be locked if needed following a specific sequence in order to avoid spurious writing to the i/o registers. the i/o controller is connected to a dedicated io bus with a toggling speed of up to 32 mhz. extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 29 edge det ector lines used to generate interrupt/event requests. each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the in ternal apb2 clock period. up to 84 gpios can be connected to the 16 configurable interr upt/event lines. the 13 other lines are connected to pvd, rtc, usarts, i2c, lpuart, lptimer or comparator events. docid027101 rev 3 25/136 stm32l071xx functional overview 32 3.8 memories the stm32l071xx devices hav e the following features: ? 20 kbytes of embedded sram accessed (r ead/write) at cpu clock speed with 0 wait states. with the enhanced bus matrix, op erating the ram does not lead to any performance penalty during accesses to th e system bus (ahb and apb buses). ? the non-volatile memory is divided into three arrays: ? 64, 128 or 192 kbytes of embedded flash program memory ? 6 kbytes of data eeprom ? information block containing 32 user and factory options bytes plus 8 kbytes of system memory flash program and data eeprom are divided into two banks. this allows writing in one bank while running code or reading data from the other bank. the user options bytes are used to write-pr otect or read-out protect the memory (with 4 kbyte granularity) and/or readout-protect the whole memory with the following options: ? level 0 : no protection ? level 1 : memory readout protected. the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2 : chip readout protected, debug features (cortex-m0+ serial wire) and boot in ram selection disabled (debugline fuse) the firewall protects parts of code/data from acce ss by the rest of the code that is executed outside of the protected area. the granularit y of the protected code segment or the non- volatile data segment is 256 bytes (flash memory or eeprom) against 64 bytes for the volatile data segment (ram). the whole non-volatile memory embeds th e error correction code (ecc) feature. 3.9 boot modes at startup, boot0 pin and nboot1 option bit are used to select one of three boot options: ? boot from flash memory ? boot from system memory ? boot from embedded ram the boot loader is located in system memory. it is used to reprogram the flash memory by using spi1(pa4, pa5, pa6, pa7) or spi2 (pb12, pb13, pb14, pb15), i2c1 (pb6, pb7) or i2c2 (pb10, pb11), usart1(pa9, pa10) or usart2(pa2, pa3). see stm32? microcontroller system memory boot mode an2606 for details. functional overview stm32l071xx 26/136 docid027101 rev 3 3.10 direct memory access (dma) the flexible 7-channel, general-purpose dma is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, lpuart, general-purpose timers, and adc. 3.11 analog-to-digital converter (adc) a native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital converter is embedded into stm32l071xx device. it has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference). three channels, pa0, pa4 and pa5, are fast channels, while the others are standard channels. the adc performs conversions in single-shot or scan mode. in sc an mode, automatic conversion is performed on a selected group of analog inputs. the adc frequency is independent from t he cpu frequency, allo wing maximum sampling rate of 1.14 msps even with a low cpu spee d. the adc consumption is low at all frequencies (~25 a at 10 ksps, ~240 a at 1msps). an auto-shutdown function guarantees that the adc is powered off ex cept during the active conversion phase. the adc can be served by the dma controller. it can operate from a supply voltage down to 1.65 v. the adc features a hardware oversampler up to 256 samples, this improves the resolution to 16 bits (see an2668). an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all scanned channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (timx) can be internally connected to the adc start triggers, to allow the application to synchronize a/d conversions and timers. 3.12 temperature sensor the temperature sensor (t sense ) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in18 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. docid027101 rev 3 27/136 stm32l071xx functional overview 32 to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.12.1 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally con nected to the adc_in17 input channel. it enables accurate monitoring of the v dd value (when no external voltage, v ref+ , is available for adc). the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memo ry area. it is accessible in read-only mode. 3.13 ultra-low-power comparators and reference voltage the stm32l071xx embed two comparators sharing the same current bias and reference voltage. the reference voltage can be internal or external (coming from an i/o). ? one comparator with ultra low consumption ? one comparator with rail-to-rail inputs, fast or slow mode. ? the threshold can be one of the following: ? external i/o pins ? internal reference voltage (v refint ) ? submultiple of internal reference voltage(1/4, 1/2, 3/4) for the rail to rail comparator. both comparators can wake up the devices from stop mode, and be combined into a window comparator. the internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 a typical). table 7. temperature sensor calibration values calibration value name description memory address tsense_cal1 ts adc raw data acquired at temperature of 30 c, ? v dda = 3 v 0x1ff8 007a - 0x1ff8 007b tsense_cal2 ts adc raw data acquired at temperature of 130 c ? v dda = 3 v 0x1ff8 007e - 0x1ff8 007f table 8. internal voltage reference measured values calibration value name description memory address vrefint_cal raw data acquired at temperature of 25 c v dda = 3 v 0x1ff8 0078 - 0x1ff8 0079 functional overview stm32l071xx 28/136 docid027101 rev 3 3.14 timers and watchdogs the ultra-low-power stm32l071xx devices include three general-purpose timers, one low- power timer (lptim), one basic timer, tw o watchdog timers and the systick timer. table 9 compares the features of the general-purpose and basic timers. 3.14.1 general-purpose timers (t im2, tim3, tim21 and tim22) there are four synchronizable general-purpose timers embedded in the stm32l071xx device (see table 9 for differences). tim2, tim3 tim2 and tim3 are based on 16-bit auto-reload up/down counter. it includes a 16-bit prescaler. it features four independent cha nnels each for input capture/output compare, pwm or one-pulse mode output. the tim2/tim3 general-purpose timers can wo rk together or with the tim21 and tim22 general-purpose timers via the timer link fe ature for synchronization or event chaining. their counter can be frozen in debug mode. an y of the general-purpose timers can be used to generate pwm outputs. tim2/tim3 have independent dma request generation. these timers are capable of handling quadrat ure (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. tim21 and tim22 tim21 and tim22 are based on a 16-bit auto-r eload up/down counter. they include a 16-bit prescaler. they have two independent channels for input capture/output compare, pwm or one-pulse mode output. they can work together and be synchronized with the tim2/tim3, full-featured general-purpose timers. they can also be used as simple time bases and be clocked by the lse clock source (32.768 khz) to provide time bases independent from the main cpu clock. table 9. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim2, tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim21, tim22 16-bit up, down, up/down any integer between 1 and 65536 no 2 no tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no docid027101 rev 3 29/136 stm32l071xx functional overview 32 3.14.2 low-power timer (lptim) the low-power timer has an independent clock and is running also in stop mode if it is clocked by lse, lsi or an external clock. it is able to wakeup the devices from stop mode. this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous / one shot mode ? selectable software / hardware input trigger ? selectable clock source ? internal clock source: l se, lsi, hsi or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by the pulse counter application) ? programmable digital glitch filter ? encoder mode 3.14.3 basic timer (tim6, tim7) these timers can be used as a generic 16-bit timebase. 3.14.4 systick timer this timer is dedicated to the os, but could also be used as a standard downcounter. it is based on a 24-bit downcounter with autore load capability and a programmable clock source. it features a maskable system interr upt generation when the counter reaches ?0?. 3.14.5 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 37 khz internal rc and, as it operates independently of the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. the counter can be frozen in debug mode. 3.14.6 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. functional overview stm32l071xx 30/136 docid027101 rev 3 3.15 communication interfaces 3.15.1 i 2 c bus up to three i 2 c interfaces (i2c1 and i2c3) can operate in multimaster or slave modes. each i 2 c interface can support standard mode (sm, up to 100 kbit/s), fast mode (fm, up to 400 kbit/s) and fast mode plus (fm+, up to 1 mbit/s) with 20 ma output drive on some i/os. 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) are also supported as we ll as programmable analog and digital noise filters. in addition, i2c1 and i2c3 provide hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify prot ocol, hardware crc ( pec) generation/verification, timeouts verifications and alert protocol management. i2c1/i2c3 also have a clock domain independent from the cpu clock, allowing the i2c1/i2c3 to wake up the mcu from stop mode on address match. each i2c interface can be served by the dma controller. refer to table 11 for an overview of i2c interface features. table 10. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. ? 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 11. stm32l071xx i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 i2c3 7-bit addressing mode x x x 10-bit addressing mode x x x standard mode (up to 100 kbit/s) x x x fast mode (up to 400 kbit/s) x x x fast mode plus with 20 ma output drive i/os (up to 1 mbit/s) xx (2) 2. see table 15: stm32l071xxx pin definition on page 39 for the list of i/os that feature fast mode plus capability x independent clock x - x smbus x - x wakeup from stop x - x docid027101 rev 3 31/136 stm32l071xx functional overview 32 3.15.2 universal synchronous/asynchr onous receiver tran smitter (usart) the four usart interfaces (usart1, usart2, usart4 and usart5) are able to communicate at speeds of up to 4 mbit/s. they provide hardware management of the cts, rts and rs485 driver enable (de) signals, multiprocessor co mmunication mode, master synchronous communication and single-wire half-duplex communication mode. usart1 and usart2 also support smartcard communication (iso 7816), irda si r endec, lin master/slave capability, auto baud rate feature and has a clock domain independent from the cpu clock, allowing to wake up the mcu from stop mode using baudrates up to 42 kbaud. all usart interfaces can be served by the dma controller. table 12 for the supported modes and features of usart interfaces. 3.15.3 low-power universal asynchron ous receiver transmitter (lpuart) the devices embed one low-power uart. the lpuart supports asynchronous serial communication with minimum power consumption. it supports half duplex single wire communication and modem operations (c ts/rts). it allows multiprocessor communication. the lpuart has a clock domain independent from the cpu clock. it can wake up the system from stop mode using baudrates up to 46 kbaud. the wakeup events from stop mode are programmable and can be: ? start bit detection ? or any received data frame ? or a specific programmed data frame table 12. usart implementation usart modes/features (1) 1. x = supported. usart1 and usart2 u sart4 and usart5 hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode (2) 2. this mode allows using the usart as an spi master. xx smartcard mode x - single-wire half-duplex communication x x irda sir endec block x - lin mode x - dual clock domain and wakeup from stop mode x - receiver timeout interrupt x - modbus communication x - auto baud rate detection (4 modes) x - driver enable x x functional overview stm32l071xx 32/136 docid027101 rev 3 only a 32.768 khz clock (lse) is needed to allow lpuart communication up to 9600 baud. therefore, even in stop mode, the lpuart can wait for an incoming frame while having an extremely low energy consumption. higher speed clock can be used to reach higher baudrates. lpuart interface can be served by the dma controller. 3.15.4 serial peripheral interface (spi)/inter-integrated sound (i2s) up to two spis are able to communicate at up to 16 mbits/s in slave and master modes in full-duplex and half-duplex communication mo des. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification support s basic sd card/mmc modes. the usarts with synchronous capabilit y can also be used as spi master. one standard i2s interfaces (multi plexed with spi2) is available. it can operate in master or slave mode, and can be configured to operate wit h a 16-/32-bit resolution as input or output channels. audio sampling frequencies from 8 khz up to 192 khz are supported. when the i2s interfaces is configured in master mode, th e master clock can be output to the external dac/codec at 256 times the sampling frequency. the spis can be served by the dma controller. refer to table 13 for the differences between spi1 and spi2. 3.16 cyclic redundancy che ck (crc) calculation unit the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. 3.17 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. table 13. spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 hardware crc calculation x x i2s mode - x ti mode x x docid027101 rev 3 33/136 stm32l071xx pin descriptions 51 4 pin descriptions figure 3. stm32l071xx lqfp100 pinout - 14 x 14 mm 1. the above figure shows the package top view. 2. i/o supplied by vddio2. 0 6 y 9 9 ' ' 3 ( 3 ( 3 ( 3 ( 3 ( 9 ' ' 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 3 + 3 + 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 5 ( ) 3 $ 3 $ 3 $ 9 ' ' , 2 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 $ 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 3 % 9 6 6 9 ' ' 9 ' ' 9 6 6 3 ( 3 ( 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 & 3 & 3 & 3 $ 3 $ / 4 ) 3 3 & 3 + 2 6 & b 2 8 7 9 ' ' $ 9 ' ' pin descriptions stm32l071xx 34/136 docid027101 rev 3 figure 4. stm32l071xx ufbga100 ballout - 7x 7 mm 1. the above figure shows the package top view. 2. i/o supplied by vddio2. figure 5. stm32l071xx lqfp64 pinout - 10 x 10 mm 1. the above figure shows the package top view. 2. i/o supplied by vddio2. 0 6 y 9 ?? ? : < > e?? & ' , d 3 + 2 6 & b , 1 9 ' ' 3 & 3 + 3 + 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 3 & 9 5 ( ) 3 & 3 $ 3 $ 9 5 ( ) 3 ' 3 $ 3 $ 3 $ 3 & 3 % 3 % 3 ( 3 ( 3 ' 3 ( 3 ( 3 ( 3 ( 3 % 3 ( 3 % 3 ( 3 % 3 ' 3 ' 3 ' 9 ' ' , 2 9 ' ' 3 ' 3 % 3 ( 3 ( 3 % % 2 2 7 3 ' 3 ' 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % w ? 3 ( 3 & 3 ( 3 ( 9 ' ' 3 % 3 ' 3 ' 3 & 9 ' ' 3 $ 3 & 3 $ 3 $ 9 6 6 3 ( 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' 9 6 6 3 & 3 & 3 & 9 6 6 9 6 6 3 + 3 & 3 ' 3 % 3 % 3 % 3 ' 3 & 3 $ 9 ' ' $ 3 $ 3 $ 3 ( e ? ? ?? ?? ? ? ?? ?e ?? ?? ? ? e? e? e e e? ee e? e? e e ?? ?? ? ? ?? ?e ?? ? ? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? ?? ? ? e ? ? ? ? ? e ? s w ? w er k ^ ??z / e w ?r k ^ ??z k h d w , r k ^ z / e w ,r k ^ z k h d e z ^ d w w w ? w ? s ^ ^ s w w w ? s s ^ ^ w ? w ? k k d w w w ? w e w ? w ? w ? w w w ? w e s / k? s ^ ^ w ? w ? w w w ? w ? w ? w ? w w w ? w e w ? w ? w ? s ^ ^ s w e w ? w w w e w ? w w w ? w w s ^ ^ s > y & we 0 6 y 9 docid027101 rev 3 35/136 stm32l071xx pin descriptions 51 figure 6. stm32l071xx tfbga64 ballout - 5x 5 mm 1. the above figure shows the package top view. 2. i/o supplied by vddio2. 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 0 6 y 9 $ % & ' ( ) * + 3 + 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 5 ( ) 9 ' ' $ 3 & 9 ' ' 9 6 6 9 ' ' 3 & 3 & 3 $ 3 $ 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 % % 2 2 7 3 ' 3 & 3 & 3 $ 3 % 3 % 3 & 3 $ 3 $ 3 $ 3 % 9 6 6 9 6 6 9 6 6 3 $ 3 & 3 & 9 ' ' 9 ' ' 9 ' ' , 2 3 & 3 & 3 $ 3 $ 3 % 3 & 3 % 3 % 3 $ 3 $ 3 % 3 % 3 % 3 % 3 $ 3 $ 3 & 3 & 3 % 3 % pin descriptions stm32l071xx 36/136 docid027101 rev 3 figure 7. stm32l071xx wlcsp49 ballout 1. the above figure shows the package top view. 2. i/o supplied by vddio2. 3 $ 9 ' ' , 2 0 6 y 9 $ % & ' ( ) 3 $ 3 $ 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 ( 3 % 3 % % 2 2 7 9 ' ' 3 % 3 % 3 % 3 & 3 % 3 & 3 & 3 & 2 6 & b 2 8 7 3 % 9 6 6 1 5 6 7 3 + 2 6 & b 2 8 7 3 % 3 $ 3 $ 3 & 3 % 3 $ 3 $ 9 ' ' $ 3 % 9 ' ' 3 & 2 6 & b , 1 3 + 2 6 & b , 1 9 5 ( ) 3 $ * 3 % 9 ' ' 3 % 3 % 3 $ 3 $ 3 $ docid027101 rev 3 37/136 stm32l071xx pin descriptions 51 figure 8. stm32l071xx lqfp48 pinout - 7 x 7 mm 1. the above figure shows the package top view. 2. i/o supplied by vddio2. figure 9. stm32l071xx lqfp32 pinout 1. the above figure shows the package top view. 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 ' ' , 2 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 ' ' 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 + 2 6 & b , 1 3 + 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ / 4 ) 3 0 6 9 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 9 6 6 % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' / 4 ) 3 pin descriptions stm32l071xx 38/136 docid027101 rev 3 figure 10. stm32l071xx ufqfpn32 pinout 1. the above figure shows the package top view. 2. i/o supplied by vddio2. 0 6 y 9 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 9 ' ' , 2 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 1 5 6 7 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 % 2 2 7 3 % 3 % 3 % 3 % 3 $ 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 9 ' ' 9 6 6 9 6 6 $ table 14. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets be low the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers docid027101 rev 3 39/136 stm32l071xx pin descriptions 51 table 15. stm32l071xxx pin definition pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 - - - - - - 1 b2 pe2 i/o ft - tim3_etr - - - - - - - 2 a1 pe3 i/o ft - tim22_ch1, tim3_ch1 - - - - - - - 3 b1 pe4 i/o ft - tim22_ch2, tim3_ch2 - - - - - - - 4 c2 pe5 i/o ft - tim21_ch1, tim3_ch3 - - - - - - - 5 d2 pe6 i/o ft - tim21_ch2, tim3_ch4 rtc_tamp3/wkup3 1 - 1 1 b2 b6 6 e2 vdd s - - - - - 2 2 a2 b7 7 c1 pc13 i/o ft - - rtc_tamp1/ rtc_ts/ rtc_out/wkup2 21 3 3a1c68d1 pc14- osc32_in (pc14) i/o ft - - osc32_in 32 4 4b1c79e1 pc15- osc32_out (pc15) i/o tc - - osc32_out ------10f2 ph9 i/oft- - - ------11g2ph10i/oft- - - - - 5 5 c1 d6 12 f1 ph0-osc_in (ph0) i/o tc - - osc_in - - 6 6 d1 d7 13 g1 ph1- osc_out (ph1) i/o tc - - osc_out 4 3 7 7 e1 d5 14 h2 nrst i/o - - - - - - - 8 e3 c5 15 h1 pc0 i/o ftf - lptim1_in1, eventout, lpuart1_rx, i2c3_scl adc_in10 - - - 9 e2 c4 16 j2 pc1 i/o ftf - lptim1_out, eventout, lpuart1_tx, i2c3_sda adc_in11 -- -10f2e717j3 pc2 i/oftf- lptim1_in2, spi2_miso/i2s2_mck adc_in12 pin descriptions stm32l071xx 40/136 docid027101 rev 3 -- -11- -18k2 pc3 i/oft- lptim1_etr, spi2_mosi/i2s2_sd adc_in13 - 4 8 12 f1 - 19 j1 vssa s - - - ------20k1 vref- s - - - - - - - g1 e6 21 l1 vref+ s - - - 5 5 9 13 h1 f7 22 m1 vdda s - - - 6 6 10 14 g2 e5 23 l2 pa0 i/o tta - tim2_ch1, usart2_cts, tim2_etr, usart4_tx, comp1_out comp1_inm, adc_in0, rtc_tamp2/wkup1 7 7 11 15 h2 e4 24 m2 pa1 i/o ft - eventout, tim2_ch2, usart2_rts_de, tim21_etr, usart4_rx comp1_inp, adc_in1 8 8 12 16 f3 f6 25 k3 pa2 i/o ft - tim21_ch1, tim2_ch3, usart2_tx, lpuart1_tx, comp2_out comp2_inm, adc_in2 9 9 13 17 g3 g7 26 l3 pa3 i/o ft - tim21_ch2, tim2_ch4, usart2_rx, lpuart1_rx comp2_inp, adc_in3 - - - 18 c2 - 27 d3 vss s - - - - -- -19d2-28h3 vdd s - - - - 10 10 14 20 h3 f5 29 m3 pa4 i/o tc - spi1_nss, usart2_ck, tim22_etr comp1_inm, comp2_inm, adc_in4 11 11 15 21 f4 g6 30 k4 pa5 i/o tc - spi1_sck, tim2_etr, tim2_ch1 comp1_inm, comp2_inm, adc_in5 table 15. stm32l071xxx pi n definition (continued) pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 docid027101 rev 3 41/136 stm32l071xx pin descriptions 51 12 12 16 22 g4 g5 31 l4 pa6 i/o ft - spi1_miso, tim3_ch1, lpuart1_cts, tim22_ch1, eventout, comp1_out adc_in6 13 13 17 23 h4 f4 32 m4 pa7 i/o ft - spi1_mosi, tim3_ch2, tim22_ch2, eventout, comp2_out adc_in7 - - - 24 h5 - 33 k5 pc4 i/o ft - eventout, lpuart1_tx adc_in14 - - - 25 h6 - 34 l5 pc5 i/o ft - lpuart1_rx adc_in15 14 14 18 26 f5 g4 35 m5 pb0 i/o ft - eventout, tim3_ch3 adc_in8, vref_out 15 15 19 27 g5 d3 36 m6 pb1 i/o ft - tim3_ch4, lpuart1_rts_de adc_in9, vref_out - - 20 28 g6 e3 37 l6 pb2 i/o ft - lptim1_out, i2c3_smba - ------38m7 pe7 i/oft- usart5_ck/usart5_ rts_de - - - - - - - 39 l7 pe8 i/o ft - usart4_tx - ------40m8 pe9 i/oft- tim2_ch1, tim2_etr, usart4_rx - ------41l8 pe10 i/oft- tim2_ch2, usart5_tx - ------42m9 pe11 i/oft- tim2_ch3, usart5_rx - - - - - - - 43 l9 pe12 i/o ft - tim2_ch4, spi1_nss - ------44m10 pe13 i/oft- spi1_sck - - - - - - - 45 m11 pe14 i/o ft - spi1_miso - - - - - - - 46 m12 pe15 i/o ft - spi1_mosi - table 15. stm32l071xxx pi n definition (continued) pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 pin descriptions stm32l071xx 42/136 docid027101 rev 3 - - 21 29 g7 g3 47 l10 pb10 i/o ft - tim2_ch3, lpuart1_tx, spi2_sck, i2c2_scl, lpuart1_rx - - - 22 30 h7 f3 48 l11 pb11 i/o ft - eventout, tim2_ch4, lpuart1_rx, i2c2_sda, lpuart1_tx - 16 16 23 31 d6 d4 49 f12 vss s - - - 17 17 24 32 e6 g2 50 g12 vdd s - - - - - 25 33 h8 g1 51 l12 pb12 i/o ft - spi2_nss/i2s2_ws, lpuart1_rts_de, i2c2_smba, eventout - - - 26 34 g8 f2 52 k12 pb13 i/o ftf - spi2_sck/i2s2_ck, mco, lpuart1_cts, i2c2_scl, tim21_ch1 - - - 27 35 f8 f1 53 k11 pb14 i/o ftf - spi2_miso/i2s2_mck, rtc_out, lpuart1_rts_de, i2c2_sda, tim21_ch2 - - - 28 36 f7 e1 54 k10 pb15 i/o ft - spi2_mosi/i2s2_sd, rtc_refin - - - - - - - 55 k9 pd8 i/o ft - lpuart1_tx - ------56k8 pd9 i/oft- lpuart1_rx - - - - - - - 57 j12 pd10 i/o ft - - - - - - - - 58 j11 pd11 i/o ft - lpuart1_cts - - - - - - - 59 j10 pd12 i/o ft - lpuart1_rts_de - - - - - - - 60 h12 pd13 i/o ft - - ------61h11 pd14 i/oft- - - - - - - - 62 h10 pd15 i/o ft - - - - - 37 f6 - 63 e12 pc6 i/o ft - tim22_ch1, tim3_ch1 - - - - 38 e7 - 64 e11 pc7 i/o ft - tim22_ch2, tim3_ch2 - table 15. stm32l071xxx pi n definition (continued) pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 docid027101 rev 3 43/136 stm32l071xx pin descriptions 51 - - - 39 e8 - 65 e10 pc8 i/o ft - tim22_etr, tim3_ch3 - - - - 40 d8 - 66 d12 pc9 i/o ftf - tim21_etr, tim3_ch4, i2c3_sda - 18 18 29 41 d7 d1 67 d11 pa8 i/o ftf - mco, eventout, usart1_ck, i2c3_scl - 19 19 30 42 c7 e2 68 d10 pa9 i/o ftf - mco, usart1_tx, i2c1_scl, i2c3_smba - 20 20 31 43 c6 c1 69 c12 pa10 i/o ftf - usart1_rx, i2c1_sda - 21 21 32 44 c8 d2 70 b12 pa11 i/o ft - spi1_miso, eventout, usart1_cts, comp1_out - 22 22 33 45 b8 b1 71 a12 pa12 i/o ft - spi1_mosi, eventout, usart1_rts_de, comp2_out - 23 23 34 46 a8 c2 72 a11 pa13 i/o ft - swdio, lpuart1_rx - ------73c11 vdd s - - - - - 35 47 d5 - 74 f11 vss s - - - - 24 36 48 e5 a1 75 g11 vddio2 s - - - 24 25 37 49 a7 b2 76 a10 pa14 i/o ft - swclk, usart2_tx, lpuart1_tx - 25 - 38 50 a6 a2 77 a9 pa15 i/o ft - spi1_nss, tim2_etr, eventout, usart2_rx, tim2_ch1, usart4_rts_de - -- -51b7-78b11 pc10 i/oft- lpuart1_tx, usart4_tx - -- -52b6-79c10 pc11 i/oft- lpuart1_rx, usart4_rx - -- -53c5-80b10 pc12 i/oft- usart5_tx, usart4_ck - table 15. stm32l071xxx pi n definition (continued) pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 pin descriptions stm32l071xx 44/136 docid027101 rev 3 ------81c9 pd0 i/oft- tim21_ch1, spi2_nss/i2s2_ws - - - - - - - 82 b9 pd1 i/o ft - spi2_sck/i2s2_ck - -- -54b5-83c8 pd2 i/oft- lpuart1_rts_de, tim3_etr, usart5_rx - ------84b8 pd3 i/oft- usart2_cts, spi2_miso/i2s2_mck - ------85b7 pd4 i/oft- usart2_rts_de, spi2_mosi/i2s2_sd - ------86a6 pd5 i/oft- usart2_tx - ------87b6 pd6 i/oft- usart2_rx - ------88a5 pd7 i/oft- usart2_ck, tim21_ch2 - 26 - 39 55 a5 a3 89 a8 pb3 i/o ft - spi1_sck, tim2_ch2, eventout, usart1_rts_de, usart5_tx comp2_inm 27 26 40 56 a4 b3 90 a7 pb4 i/o ftf - spi1_miso, tim3_ch1, tim22_ch1, usart1_cts, usart5_rx, i2c3_sda comp2_inp 28 27 41 57 c4 a4 91 c5 pb5 i/o ft - spi1_mosi, lptim1_in1, i2c1_smba, tim3_ch2/tim22_ch2, usart1_ck, usart5_ck/usart5_ rts_de comp2_inp 29 28 42 58 d3 b4 92 b5 pb6 i/o ftf - usart1_tx, i2c1_scl, lptim1_etr, comp2_inp table 15. stm32l071xxx pi n definition (continued) pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 docid027101 rev 3 45/136 stm32l071xx pin descriptions 51 30 29 43 59 c3 c3 93 b4 pb7 i/o ftf - usart1_rx, i2c1_sda, lptim1_in2, usart4_cts comp2_inp, vref_pvd_in 31 30 44 60 b4 a5 94 a4 boot0 i - - - - - 45 61 b3 b5 95 a3 pb8 i/o ftf - i2c1_scl - - - 46 62 a3 a6 96 b3 pb9 i/o ftf - eventout, i2c1_sda, spi2_nss/i2s2_ws - - - - - - - 97 c3 pe0 i/o ft - eventout - - - - - - - 98 a2 pe1 i/o ft - eventout - 32 31 47 63 d4 - 99 d3 vss s - - - -324864e4a7100c4 vdd s - - - 1. ufqfpn32 pinout differs from other stm32 devices except stm32l07xxx and stm32l8xxx. table 15. stm32l071xxx pi n definition (continued) pin number pin name (function after reset) pin type i/o structure note alternate functions a dditional functions lqfp32 ufqfpn32 (1) lqfp48 lqfp64 ufbga64 wlcsp49 lqfp100 ufbg100 pin descriptions stm32l071xx 46/136 docid027101 rev 3 table 16. alternate functions port a port af0 af1 af2 af3 af4 af5 af6 af7 spi1/spi2/i2s2/u sart1/2/ lpuart1/lptim 1/ tim2/21/22/ eventout/ sys_af spi1/spi2/i2s2/i2 c1/tim2/21 spi1/spi2/i2s2/l puart1/ usart5/lptim1 /tim2/3/evento ut/ sys_af i2c1/ eventout i2c1/usart1/2/ lpuart1/ tim3/22/ eventout spi2/i2s2/i2c2/u sart1/ tim2/21/22 i2c1/2/ lpuart1/ usart4/ uasrt5/tim21/e ventout i2c3/lpuart1/c omp1/2/ tim3 port a pa0 - - tim2_ch1 usart2_cts tim2_etr usart4_tx comp1_out pa1 eventout tim2_ch2 usart2_rts_d e tim21_etr usart4_rx - pa2 tim21_ch1 tim2_ch3 usart2_tx - lpuart1_tx comp2_out pa3 tim21_ch2 tim2_ch4 usart2_rx - lpuart1_rx - pa4 spi1_nss - - usart2_ck tim22_etr - - pa5 spi1_sck - tim2_etr tim2_ch1 - - pa6 spi1_miso tim3_ch1 lpuart1_cts tim22_ch1 eventout comp1_out pa7 spi1_mosi tim3_ch2 - tim22_ch2 eventout comp2_out pa8 mco eventout usart1_ck - - i2c3_scl pa9 mco - usart1_tx - i2c1_scl i2c3_smba pa10 - - usart1_rx - i2c1_sda - pa11 spi1_miso - eventout usart1_cts - - comp1_out pa12 spi1_mosi - eventout usart1_rts_ de - - comp2_out pa13 swdio - - - - lpuart1_rx - pa14 swclk - - - usart2_tx - lpuart1_tx - pa15 spi1_nss tim2_etr eventout usart2_rx tim2_ch1 usart4_rts_d e - stm32l071xx pin descriptions docid027101 rev 3 47/136 table 17. alternate functions port b port af0 af1 af2 af3 af4 af5 af6 af7 spi1/spi2/i2s2/ usart1/2/ lpuart1/ lptim1/ tim2/21/22/ eventout/ sys_af spi1/spi2/i2s2/i 2c1/tim2/21 spi1/spi2/i2s2/ lpuart1/ usart5/lptim 1/tim2/3/event out/ sys_af i2c1/ eventout i2c1/usart1/2/ lpuart1/ tim3/22/ eventout spi2/i2s2/i2c2/ usart1/ tim2/21/22 i2c1/2/ lpuart1/ usart4/ uasrt5/tim21/ eventout i2c3/lpuart1/ comp1/2/ tim3 port b pb0 eventout tim3_ch3 - - - - pb1 - tim3_ch4 lpuart1_rts_de - - - pb2 - - lptim1_out - - - i2c3_smba pb3 spi1_sck tim2_ch2 eventout usart1_rts_de usart5_tx - pb4 spi1_miso tim3_ch1 tim22_ch1 usart1_cts usart5_rx i2c3_sda pb5 spi1_mosi lptim1_in1 i2c1_smba tim3_ch2/ tim22_ch2 usart1_ck usart5_ck/ usart5_rts_d e - pb6 usart1_tx i2c1_scl lptim1_etr - - - - pb7 usart1_rx i2c1_sda lptim1_in2 - - usart4_cts - pb8 - - i2c1_scl - - - pb9 - eventout - i2c1_sda spi2_nss/ i2s2_ws -- pb10 - tim2_ch3 lpuart1_tx spi2_sck i2c2_scl lpuart1_rx pb11 eventout tim2_ch4 lpuart1_rx - i2c2_sda lpuart1_tx pb12 spi2_nss/i2s2_ws lpuart1_rts_ de i2c2_smba eventout - pb13 spi2_sck/i2s2_ck mco lpuart1_cts i2c2_scl tim21_ch1 - pb14 spi2_miso/ i2s2_mck rtc_out lpuart1_rts_de i2c2_sda tim21_ch2 - pb15 spi2_mosi/ i2s2_sd rtc_refin - - - - - pin descriptions stm32l071xx 48/136 docid027101 rev 3 table 18. alternate functions port c port af0 af1 af2 af3 af4 af5 af6 af7 spi1/spi2/i2s2/ usart1/2/ lpuart1/ lptim1/ tim2/21/22/ eventout/ sys_af spi1/spi2/i2s2/i2c1/ tim2/21 spi1/spi2/i2s2/ lpuart1/ usart5/ lptim1/tim2/3 /eventout/sys_af i2c1/ eventout i2c1/usart1/2/ lpuart1/ tim3/22/ eventout spi2/i2s2 /i2c2/ usart1/ tim2/21/22 i2c1/2/ lpuart1/ usart4/ uasrt5/tim21/e ventout i2c3/lpuart1/ comp1/2/ tim3 port c pc0 lptim1_in1 eventout lpuart1_rx i2c3_scl pc1 lptim1_out eventout lpuart1_tx i2c3_sda pc2 lptim1_in2 spi2_miso/ i2s2_mck pc3 lptim1_etr spi2_mosi/ i2s2_sd pc4 eventout lpuart1_tx pc5 lpuart1_rx pc6 tim22_ch1 tim3_ch1 pc7 tim22_ch2 tim3_ch2 pc8 tim22_etr tim3_ch3 pc9 tim21_etr tim3_ch4 i2c3_sda pc10 lpuart1_tx usart4_tx pc11 lpuart1_rx usart4_rx pc12 usart5_tx usart4_ck pc13 pc14 pc15 stm32l071xx pin descriptions docid027101 rev 3 49/136 table 19. alternate functions port d port af0 af1 af2 af3 af4 af5 af6 af7 spi1/spi2/i2s2/ usart1/2/ lpuart1/ lptim1/ tim2/21/22/ eventout/ sys_af spi1/spi2/i2s2/i2c1/ tim2/21 spi1/spi2/i2s2/ lpuart1/ usart5/ lptim1/tim2/3 /eventout/ sys_af i2c1/ eventout i2c1/usart1/2/ lpuart1/ tim3/22/ eventout spi2/i2s2 /i2c2/ usart1/ tim2/21/22 i2c1/2/ lpuart1/ usart4/ uasrt5/tim21/e ventout i2c3/lpuart1/ comp1/2/tim3 port d pd0 tim21_ch1 spi2_nss/i2s2_ws - - - - - - pd1 - spi2_sck/i2s2_ck - - - - - - pd2 lpuart1_rts_ de tim3_etr - - - usart5_rx - pd3 usart2_cts spi2_miso/ i2s2_mck -- - - - pd4 usart2_rts_d e spi2_mosi/i2s2_sd - - - - - - pd5 usart2_tx - - - - - - - pd6 usart2_rx - - - - - - - pd7 usart2_ck tim21_ch2 - - - - - - pd8 lpuart1_tx - - - - - - pd9 lpuart1_rx - - - - - - pd10 - - - - - - - pd11 lpuart1_cts - - - - - - pd12 lpuart1_rts_ de --- - - - pd13 - - - - - - - pd14 - - - - - - - pd15 - - - - - - pin descriptions stm32l071xx 50/136 docid027101 rev 3 table 20. alternate functions port e port af0 af1 af2 af3 af4 af5 af6 af7 spi1/spi2/i2s2/ usart1/2/ lpuart1/lpti m1/ tim2/21/22/ eventout/ sys_af spi1/spi2/i2s2/i2c1 /tim2/21 spi1/spi2/i2s2/ lpuart1/ usart5/ lptim1/tim2/3 /eventout/ sys_af i2c1/ eventout i2c1/usart1/2/ lpuart1/ tim3/22/ eventout spi2/i2s2 /i2c2/ usart1/ tim2/21/22 i2c1/2/ lpuart1/ usart4/ uasrt5/tim21/ eventout i2c3/lpuart1/ comp1/2/tim3 port e pe0 - eventout - - - - - pe1 - eventout - - - - - pe2 - tim3_etr - - - - - pe3 tim22_ch1 tim3_ch1 - - - - - pe4 tim22_ch2 - tim3_ch2 - - - - - pe5 tim21_ch1 - tim3_ch3 - - - - - pe6 tim21_ch2 - tim3_ch4 - - - - - pe7 - - - - - usart5_ck/u sart5_rts_d e - pe8 - - - - - usart4_tx - pe9 tim2_ch1 tim2_etr - - - usart4_rx - pe10 tim2_ch2 - - - - usart5_tx - pe11 tim2_ch3 - - - - - usart5_rx - pe12 tim2_ch4 - spi1_nss - - - - - pe13 - spi1_sck - - - - - pe14 - spi1_miso - - - - - pe15 - spi1_mosi - - - - - stm32l071xx pin descriptions docid027101 rev 3 51/136 table 21. alternate functions port h port af0 af1 af2 af3 af4 af5 af6 af7 spi1/spi2/ i2s2/usart1/2/ lpuart1/ lptim1/ tim2/21/22/ eventout/ sys_af spi1/spi2/i2s2 /i2c1/tim2/21 spi1/spi2/i2s2/ lpuart1/ usart5/ lptim1/tim2/3/ eventout/ sys_af i2c1/ eventout i2c1/usart1/2/ lpuart1/ tim3/22/ eventout spi2/i2s2/i2c2/ usart1/ tim2/21/22 i2c1/2/ lpuart1/ usart4/ uasrt5/tim21/ eventout i2c3/ lpuart1/ comp1/2/ tim3 port h ph0 - - - - - - - ph1 - - - - - - - - ph9 - - - - - - - - ph10 - - - - - - - - memory mapping stm32l071xx 52/136 docid027101 rev 3 5 memory mapping figure 11. memory map 1. refer to the stm32l071xx reference manual for details on the flash memory organization for each memory size. 0 6 y 9 5 h v h u y h g ) / 0 / 2 4 [ ) ) ) ) ) ) ) ) 3 h u l s k h u d o v 6 5 $ 0 ' d w d ( ( 3 5 2 0 e d q n ' d w d ( ( 3 5 2 0 e d q n ) o d v k s u r j u d p e d q n ) o d v k s u r j u d p e d q n r e s e r v e d 6 \ v w h p p h p r u \ 2 s w l r q e \ w h v [ ( & l a s h s y s t e m m e m o r y o r 3 2 ! - d e p e n d i n g o n " / / 4 c o n f i g u r a t i o n [ [ ( [ & [ $ [ [ [ [ [ [ [ ) ) ) ) ) ) ) r e s e r v e d & 2 ' ( ! 0 " ! 0 " r e s e r v e d [ [ [ [ r e s e r v e d [ ! ( " [ r e s e r v e d [ ) ) ) [ ) ) & r u w h [ 0 s h u l s k h u d o v docid027101 rev 3 53/136 stm32l071xx electrical characteristics 107 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.6 v (for the 1.65 v ?? v dd ?? 3.6 v voltage range). they are given on ly as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 12 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 13 . figure 12. pin loading conditions figure 13. pin input voltage d l f & s ) 0 & 8 s l q d l f 0 & 8 s l q 9 , 1 electrical characteristics stm32l071xx 54/136 docid027101 rev 3 6.1.6 power supply scheme figure 14. power supply scheme 6.1.7 current consumption measurement figure 15. current consum ption measurement scheme 0 6 y 9 $ q d o r j 5 & 3 / / & 2 0 3 ? 9 ' ' * 3 , 2 v 2 8 7 , 1 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v 6 w d q g e \ s r z h u f l u f x l w u \ 2 6 & 5 7 & : d n h x s o r j l f 5 7 & e d f n x s u h j l v w h u v 1 ? q ) ? ? ) 5 h j x o d w r u 9 6 6 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 6 6 $ $ ' & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) 9 5 ( ) q ) ? ) 9 ' ' $ 0 6 y 9 1 [ 9 ' ' , ' ' 1 ? q ) ? ? ) 1 [ 9 6 6 9 ' ' $ docid027101 rev 3 55/136 stm32l071xx electrical characteristics 107 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 22: voltage characteristics , table 23: current characteristics , and table 24: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 22. voltage characteristics symbol definition min max unit v dd ?v ss external main supply voltage ? (including v dda , v ddio2 v dd ) (1) 1. all main power (v dd ,, v dda ) and ground (v ss , v ssa ) pins must always be connec ted to the external power supply, in the permitted range. ?0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 23 for maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v dd +4.0 input voltage on tc pins v ss ? 0.3 4.0 input voltage on boot0 v ss v dd ?? 4.0 input voltage on any other pin v ss ?? 0.3 4.0 | ? v dd | variations between different v ddx power pins - 50 mv |v dda -v ddx | variations between any v ddx and v dda power pins (3) 3. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and device operation. v ddio2 is independent from v dd and v dda : its value does not need to respect this rule. - 300 | ? v ss | variations between all different ground pins including v ref- pin -50 v ref+ ?v dda allowed voltage difference for v ref+ > v dda -0.4v v esd(hbm) electrostatic discharge voltage ? (human body model) see section 6.3.11 electrical characteristics stm32l071xx 56/136 docid027101 rev 3 table 23. current characteristics symbol ratings max. unit i vdd (2) total current into sum of all v dd power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 105 ma i vss (2) 2. this current consumption must be correctly distri buted over all i/os and control pins. the total output current must not be sunk/sourced between two consecut ive power supply pins referring to high pin count lqfp packages. total current out of sum of all v ss ground lines (sink) (1) 105 i vddio2 total current into v ddio2 power line (source) 25 i vdd(pin) maximum current into each v dd power pin (source) (1) 100 i vss(pin) maximum current out of each v ss ground pin (sink) (1) 100 i io output current sunk by any i/o and control pin except ftf pins 16 output current sunk by ftf pins 22 output current sourced by any i/o and control pin -16 i io(pin) total output current sunk by sum of all ios and control pins except pa11 and pa12 (2) 90 total output current sunk by pa11 and pa12 25 total output current sourced by sum of all ios and control pins (2) -90 i inj(pin) injected current on ft, fff, rst and b pins -5/+0 (3) 3. positive current injection is not possible on these i/os. a negative injection is induced by v in docid027101 rev 3 57/136 stm32l071xx electrical characteristics 107 6.3 operating conditions 6.3.1 general operating conditions table 25. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 32 mhz f pclk1 internal apb1 clock frequency - 0 32 f pclk2 internal apb2 clock frequency - 0 32 v dd standard operating voltage bor detector disabled 1.65 3.6 v bor detector enabled, at power on 1.8 3.6 bor detector disabled, after power on 1.65 3.6 v dda analog operating voltage (all features) must be the same voltage as v dd (1) 1.65 3.6 v v ddio2 standard operating voltage - 1.65 3.6 v v in input voltage on ft, ftf and rst pins (2) 2.0 v ? v dd ? 3.6 v -0.3 5.5 v 1.65 v ? v dd ? 2.0 v -0.3 5.2 input voltage on boot0 pin - 0 5.5 input voltage on tc pin - -0.3 v dd +0.3 p d power dissipation at t a = 85 c (range 6) or t a =105 c (rage 7) (3) ufbga100 package - 351 mw lqfp100 package - 488 tfbga64 package - 313 lqfp64 package - 435 wlcsp49 package - 417 lqfp48 package - 370 ufqfpn32 package - 556 lqfp32 package - 333 power dissipation at t a = 125 c (range 3) (3) ufbga100 package - 88 lqfp100 package - 122 tfbga64 package - 78 lqfp64 package - 109 wlcsp49 package - 104 lqfp48 package - 93 ufqfpn32 package - 139 lqfp32 package - 83 electrical characteristics stm32l071xx 58/136 docid027101 rev 3 t a temperature range maximum power dissipation (range 6) ?40 85 c maximum power dissipation (range 7) ?40 105 maximum power dissipation (range 3) ?40 125 t j junction temperature range (range 6) -40 c ? t a ? 85 ?40 105 junction temperature range (range 7) -40 c ? t a ? 105 c ?40 125 junction temperature range (range 3) -40 c ? t a ? 125 c ?40 130 1. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and normal operation. 2. to sustain a voltage higher than v dd +0.3v, the internal pull-up/pull-down resistors must be disabled. 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max (see table 24: thermal characteristics on page 56 ). table 25. general operating conditions (continued) symbol parameter conditions min max unit docid027101 rev 3 59/136 stm32l071xx electrical characteristics 107 6.3.2 embedded reset and power control block characteristics the parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in table 25 . table 26. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd (1) v dd rise time rate bor detector enabled 0 - ? s/v bor detector disabled 0 - 1000 v dd fall time rate bor detector enabled 20 - ? bor detector disabled 0 - 1000 t rsttempo (1) reset temporization v dd rising, bor enabled - 2 3.3 ms v dd rising, bor disabled (2) 0.4 0.7 1.6 v por/pdr power on/power down reset threshold falling edge 1 1.5 1.65 v rising edge 1.3 1.5 1.65 v bor0 brown-out reset threshold 0 falling edge 1.67 1.7 1.74 rising edge 1.69 1.76 1.8 v bor1 brown-out reset threshold 1 falling edge 1.87 1.93 1.97 rising edge 1.96 2.03 2.07 v bor2 brown-out reset threshold 2 falling edge 2.22 2.30 2.35 rising edge 2.31 2.41 2.44 v bor3 brown-out reset threshold 3 falling edge 2.45 2.55 2.6 rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 falling edge 2.68 2.8 2.85 rising edge 2.78 2.9 2.95 v pvd0 programmable voltage detector threshold 0 falling edge 1.8 1.85 1.88 rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.20 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 electrical characteristics stm32l071xx 60/136 docid027101 rev 3 6.3.3 embedded internal reference voltage the parameters given in table 28 are based on characterization results, unless otherwise specified. v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 v rising edge 3.08 3.15 3.20 v hyst hysteresis voltage bor0 threshold - 40 - mv all bor and pvd thresholds excepting bor0 -100- 1. guaranteed by characterization results. 2. valid for device version without bor at power up. please see option "d" in orderi ng information scheme for more details. table 26. embedded reset and power control block characteristics (continued) symbol parameter conditions min typ max unit table 27. embedded internal reference voltage calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 25 c ? v dda = 3 v 0x1ff8 0078 - 0x1ff8 0079 table 28. embedded internal reference voltage (1) symbol parameter conditions min typ max unit v refint out (2) internal reference voltage ? 40 c < t j < +125 c 1.202 1.224 1.242 v t vrefint internal reference startup time - - 2 3 ms v vref_meas v dda and v ref+ voltage during v refint factory measure -2.9933.01v a vref_meas accuracy of factory-measured v refint value (3) including uncertainties due to adc and v dda /v ref+ values -- 5mv t coeff (4) temperature coefficient ?40 c < t j < +125 c - 25 100 ppm/c a coeff (4) long-term stability 1000 hours, t= 25 c - - 1000 ppm v ddcoeff (4) voltage coefficient 3.0 v < v dda < 3.6 v - - 2000 ppm/v t s_vrefint (4)(5) adc sampling time when reading the internal reference voltage -510-s t adc_buf (4) startup time of reference voltage buffer for adc ---10s i buf_adc (4) consumption of reference voltage buffer for adc - - 13.5 25 a i vref_out (4) vref_out output current (6) ---1a c vref_out (4) vref_out output load - - - 50 pf docid027101 rev 3 61/136 stm32l071xx electrical characteristics 107 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, temperature, i/o pin loadi ng, device software conf iguration, operating frequencies, i/o pin switching rate, program lo cation in memory and executed binary code. the current consumption is measured as described in figure 15: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equival ent to dhrystone 2.1 code if not specified otherwise. the current consumption values are derived from the tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25: general operating conditions unless otherwis e specified. the mcu is placed under the following conditions: ? all i/o pins are configured in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time and prefetch is adjusted depending on fhclk frequency and voltage range to provide t he best cpu performance unless otherwise specified. ? when the peripherals are enabled f apb1 = f apb2 = f apb ? when pll is on, the pll inputs are equal to hsi = 16 mhz (if internal clock is used) or hse = 16 mhz (if hse bypass mode is used) ? the hse user clock applied to osci_in input follows the characteristic specified in table 42: high-speed external user clock characteristics ? for maximum current consumption v dd = v dda = 3.6 v is applied to all supply pins ? for typical current consumption v dd = v dda = 3.0 v is applied to all supply pins if not specified otherwise the parameters given in table 49 , table 25 and table 26 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . i lpbuf (4) consumption of reference voltage buffer for vref_out and comp - - 730 1200 na v refint_div1 (4) 1/4 reference voltage - 24 25 26 % v refint v refint_div2 (4) 1/2 reference voltage - 49 50 51 v refint_div3 (4) 3/4 reference voltage - 74 75 76 1. refer to table 40: peripheral current c onsumption in stop and standby mode for the value of the internal reference current consumption (i refint ). 2. guaranteed by test in production. 3. the internal v ref value is individually measured in produc tion and stored in dedicated eeprom bytes. 4. guaranteed by design. 5. shortest sampling time can be determined in the application by multiple iterations. 6. to guarantee less than 1% vref_out deviation. table 28. embedded internal reference voltage (1) (continued) symbol parameter conditions min typ max unit electrical characteristics stm32l071xx 62/136 docid027101 rev 3 table 29. current consumption in run mode, code with data processing running from flash memory symbol parameter condition f hclk (mhz) typ max (1) unit i dd (run from flash memory) supply current in run mode code executed from flash memory f hse = f hclk up to 16mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range3, vcore=1.2 v vos[1:0]=11 1 190 250 a 2 345 380 4 650 670 range2, vcore=1.5 v vos[1:0]=10 4 0,8 0,86 ma 8 1,55 1,7 16 2,95 3,1 range1, vcore=1.8 v vos[1:0]=01 81,92,1 16 3,55 3,8 32 6,65 7,2 msi clock source range3, vcore=1.2 v vos[1:0]=11 0,065 39 130 a 0,524 115 210 4,2 700 770 hsi clock source (16mhz) range2, vcore=1.5 v vos[1:0]=10 16 2,9 3,2 ma range1, vcore=1.8 v vos[1:0]=01 32 7,15 7,4 1. guaranteed by characterization results at 125 c, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). table 30. current consumption in run mode vs code type, code with data processing running from flash memory symbol parameter conditions f hclk typ unit i dd (run from flash memory) supply current in run mode, code executed from flash memory f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (1) range 3, v core =1.2 v, vos[1:0]=11 dhrystone 4 mhz 650 a coremark 655 fibonacci 485 while(1) 385 while(1), 1ws, prefetch off 375 range 1, v core =1.8 v, vos[1:0]=01 dhrystone 32 mhz 6,65 ma coremark 6,9 fibonacci 6,75 while(1) 5,8 while(1), prefetch off 5,5 1. oscillator bypassed (hsebyp = 1 in rcc_cr register). docid027101 rev 3 63/136 stm32l071xx electrical characteristics 107 figure 16. i dd vs v dd , at t a = 25/55/85/105 c, run mode, code running from flash memory, range 2, hse, 1ws figure 17. i dd vs v dd , at t a = 25/55/85/105 c, run mode, code running from flash memory, range 2, hsi16, 1ws 0 6 y 9 ? & ? & ? & ? & ? & ? & , ' ' p $ 9 ' ' 9 0 6 y 9 ? & ? & ? & ? & ? & ? & , ' ' p $ 9 ' ' 9 electrical characteristics stm32l071xx 64/136 docid027101 rev 3 table 31. current consumption in run mode, code with data processing running from ram symbol parameter condition f hclk (mhz) typ max (1) unit i dd (run from ram) supply current in run mode code executed from ram, flash memory switched off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range3, vcore=1.2 v vos[1:0]=11 1175230 a 2315360 4570630 range2, vcore=1.5 v vos[1:0]=10 40,710,78 ma 81,351,6 16 2,7 3 range1, vcore=1.8 v vos[1:0]=01 81,71,9 16 3,2 3,7 32 6,65 7,1 msi clock range3, vcore=1.2 v vos[1:0]=11 0,065 38 98 a 0,524 105 160 4,2 615 710 hsi clock source (16 mhz) range2, vcore=1.5 v vos[1:0]=10 16 2,85 3 ma range1, vcore=1.8 v vos[1:0]=01 32 6,85 7,3 1. guaranteed by characterization results at 125 c , unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). table 32. current consumption in run mode vs code type, code with data processing running from ram (1) symbol parameter conditions f hclk typ unit i dd (run from ram) supply current in run mode, code executed from ram, flash memory switched off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range 3, v core =1.2 v, vos[1:0]=11 dhrystone 4 mhz 570 a coremark 670 fibonacci 410 while(1) 375 range 1, v core =1.8 v, vos[1:0]=01 dhrystone 32 mhz 6,65 ma coremark 6,95 fibonacci 5,9 while(1) 5,2 1. guaranteed by characterization re sults, unless otherwise specified. 2. oscillator bypassed (hsebyp = 1 in rcc_cr register). docid027101 rev 3 65/136 stm32l071xx electrical characteristics 107 table 33. current consumption in sleep mode symbol parameter condition f hclk (mhz) typ max (1) unit i dd (sleep) supply current in sleep mode, flash memory switched off f hse = f hclk up to 16 mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range3, vcore=1.2 v vos[1:0]=11 1 43,5 110 a 272140 4 130 200 range2, vcore=1.5 v vos[1:0]=10 4 160 220 8 305 380 16 590 690 range1, vcore=1.8 v vos[1:0]=01 8 370 460 16 715 840 32 1650 2000 msi clock range3, vcore=1.2 v vos[1:0]=11 0,065 18 93 0,524 31,5 110 4,2 140 230 hsi clock source (16 mhz) range2, vcore=1.5 v vos[1:0]=10 16 665 850 range1, vcore=1.8 v vos[1:0]=01 32 1750 2100 supply current in sleep mode, flash memory switched on f hse = f hclk up to 16mhz included, f hse = f hclk /2 above 16 mhz (pll on) (2) range3, vcore=1.2 v vos[1:0]=11 1 57,5 130 284160 4 150 220 range2, vcore=1.5 v vos[1:0]=10 4 170 240 8 315 400 16 605 710 range1, vcore=1.8 v vos[1:0]=01 8 380 470 16 730 860 32 1650 2000 msi clock range3, vcore=1.2 v vos[1:0]=11 0,065 29,5 110 0,524 44,5 120 4,2 150 240 hsi clock source (16mhz) range2, vcore=1.5 v vos[1:0]=10 16 680 930 range1, vcore=1.8 v vos[1:0]=01 32 1750 2200 1. guaranteed by characterization results at 125 c, unless otherwise specified. 2. oscillator bypassed (hseby p = 1 in rcc_cr register). electrical characteristics stm32l071xx 66/136 docid027101 rev 3 table 34. current consumption in low-power run mode symbol parameter condition f hclk (mhz) typ max (1) unit i dd (lp run) supply current in low-power run mode all peripherals off, code executed from ram, flash memory switched off, v dd from 1.65 to 3.6 v msi clock = 65 khz, f hclk = 32 khz t a = ? 40 to 25c 0,032 9,45 12 a t a = 85c 14 58 t a = 105c 21 64 t a = 125c 36,5 160 msi clock = 65 khz, f hclk = 65khz t a = ? 40 to 25c 0,065 14,5 18 t a = 85c 19,5 60 t a = 105c 26 65 t a = 125c 42 160 msi clock=131 khz, f hclk = 131 khz t a = ? 40 to 25c 0,131 26,5 30 t a = 55c 27,5 60 t a = 85c 31 66 t a = 105c 37,5 77 t a = 125c 53,5 170 all peripherals off, code executed from flash memory, vdd from 1.65 v to 3.6 v msi clock = 65 khz, f hclk = 32 khz t a = ? 40 to 25c 0,032 24,5 34 t a = 85c 30 82 t a = 105c 38,5 90 t a = 125c 58 120 msi clock = 65 khz, f hclk = 65 khz t a = ? 40 to 25c 0,065 30,5 40 t a = 85c 36,5 88 t a = 105c 45 96 t a = 125c 64,5 120 msi clock = 131 khz, f hclk = 131 khz t a = ? 40 to 25c 0,131 45 56 t a = 55c 48 96 t a = 85c 51 110 t a = 105c 59,5 120 t a = 125c 79,5 150 1. guaranteed by characterization results at 125 c, unless otherwise specified. docid027101 rev 3 67/136 stm32l071xx electrical characteristics 107 figure 18. i dd vs v dd , at t a = 25 c, low-power run mode, code running from ram, range 3, msi (range 0) at 64 khz, 0 ws 0 6 y 9 ( ( ( ( ( ( ( ( ( , ' ' p $ 9 ' ' 9 table 35. current consumption in low-power sleep mode symbol parameter condition typ max (1) unit i dd (lp sleep) supply current in low-power sleep mode all peripherals off, code executed from flash memory, v dd from 1.65 to 3.6 v msi clock = 65 khz, f hclk = 32 khz, flash memory off t a = ? 40 to 25c 4,7 - a msi clock = 65 khz, f hclk = 32 khz t a = ? 40 to 25c 17 24 t a = 85c 19,5 30 t a = 105c 23 47 t a = 125c 32,5 70 msi clock = 65 khz, f hclk = 65 khz t a = ? 40 to 25c 17 24 t a = 85c 20 31 t a = 105c 23,5 47 t a = 125c 32,5 70 msi clock = 131khz, f hclk = 131 khz t a = ? 40 to 25c 19,5 27 t a = 55c 20,5 28 t a = 85c 22,5 33 t a = 105c 26 50 t a = 125c 35 73 1. guaranteed by characterization results at 125 c, unless otherwise specified. electrical characteristics stm32l071xx 68/136 docid027101 rev 3 figure 19. i dd vs v dd , at t a = 25/55/ 85/105/125 c, stop mode with rtc enabled and running on lse low drive table 36. typical and maximum current consumptions in stop mode symbol parameter conditions typ max (1) 1. guaranteed by characterization results at 125 c, unless otherwise specified. unit i dd (stop) supply current in stop mode t a = ? 40 to 25c 0,43 1,00 a t a = 55c 0,735 2,50 t a = 85c 2,25 4,90 t a = 105c 5,3 13,00 t a = 125c 12,5 28,00 0 6 y 9 ( ( ( ( ( ( ( ( ? & ? & ? & ? & ? & ? & , ' ' p $ 9 ' ' 9 docid027101 rev 3 69/136 stm32l071xx electrical characteristics 107 figure 20. i dd vs v dd , at t a = 25/55/85/105/125 c, stop mode with rtc disabled, all clocks off 0 6 y 9 ( ( ( ( ( ( ( ? & ? & ? & ? & ? & ? & , ' ' p $ 9 ' ' 9 table 37. typical and maximum current consumptions in standby mode symbol parameter conditions typ max (1) unit i dd (standby) supply current in standby mode independent watchdog and lsi enabled t a = ? 40 to 25c 0,855 1,70 a t a = 55 c - 2,90 t a = 85 c - 3,30 t a = 105 c - 4,10 t a = 125 c - 8,50 independent watchdog and lsi off t a = ? 40 to 25c 0,29 0,60 t a = 55 c 0,32 1,20 t a = 85 c 0,5 2,30 t a = 105 c 0,94 3,00 t a = 125 c 2,6 7,00 1. guaranteed by characterization results at 125 c, unless otherwise specified electrical characteristics stm32l071xx 70/136 docid027101 rev 3 table 38. average current consumption during wakeup symbol parameter system frequency current consumption during wakeup unit i dd (wakeup from stop) supply current during wakeup from stop mode hsi 1 ma hsi/4 0,7 msi clock = 4,2 mhz 0,7 msi clock = 1,05 mhz 0,4 msi clock = 65 khz 0,1 i dd (reset) reset pin pulled down - 0,21 i dd (power-up) bor on - 0,23 i dd (wakeup from standby) with fast wakeup set msi clock = 2,1 mhz 0,5 with fast wakeup disabled msi clock = 2,1 mhz 0,12 docid027101 rev 3 71/136 stm32l071xx electrical characteristics 107 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in the following tables. the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on table 39. peripheral current consumption in run or sleep mode (1) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core =1.8 v vos[1:0] = 01 range 2, v core =1.5 v vos[1:0] = 10 range 3, v core =1.2 v vos[1:0] = 11 low-power sleep and run apb1 crs 2.5 2 2 2 a/mhz (f hclk ) i2c1 11 9.5 7.5 9 i2c3 11 9 7 9 lptim1 10 8.5 6.5 8 lpuart1 8 6.5 5.5 6 spi2 9 4.5 3.5 4 usart2 14.5 12 9.5 11 usart4 5 4 3 5 usart5 5 4 3 5 tim2 10.5 8.5 7 9 tim3 12 10 8 11 tim6 3.5 3 2.5 2 tim7 3.5 3 2.5 2 wwdg 3 2 2 2 apb2 adc1 (2) 5.5 5 3.5 4 a/mhz (f hclk ) spi1 4 3 3 2.5 usart1 14.5 11.5 9.5 12 tim21 7.5 6 5 5.5 tim22 7 6 5 6 firewall 1.5 1 1 0.5 dbgmcu 1.5 1 1 0.5 syscfg 2.5 2 2 1.5 electrical characteristics stm32l071xx 72/136 docid027101 rev 3 cortex- m0+ core i/o port gpioa 3.5 3 2.5 2.5 a/mhz (f hclk ) gpiob 3.5 2.5 2 2.5 gpioc 8.5 6.5 5.5 7 gpiod 1 0.5 0.5 0.5 gpioe 8 6 5 6 gpioh 1.5 1 1 0.5 ahb crc 1.5 1 1 1 a/mhz (f hclk ) flash 0 (3) 0 (3) 0 (3) 0 (3) dma1 10 8 6.5 8.5 all enabled 204 162 130 202 a/mhz (f hclk ) pwr 2.5 2 2 1 a/mhz (f hclk ) 1. data based on differential i dd measurement between all peripheral s off an one peripheral with clock enabled, in the following conditions: f hclk = 32 mhz (range 1), f hclk = 16 mhz (range 2), f hclk = 4 mhz (range 3), f hclk = 64khz (low-power run/sleep), f apb1 = f hclk , f apb2 = f hclk , default prescaler value for each peripheral. the cpu is in sleep mode in both cases. no i/o pins toggling. not tested in production. 2. hsi oscillator is off for this measure. 3. current consumption is negligible and close to 0 a. table 39. peripheral current consumption in run or sleep mode (1) (continued) peripheral typical consumption, v dd = 3.0 v, t a = 25 c unit range 1, v core =1.8 v vos[1:0] = 01 range 2, v core =1.5 v vos[1:0] = 10 range 3, v core =1.2 v vos[1:0] = 11 low-power sleep and run docid027101 rev 3 73/136 stm32l071xx electrical characteristics 107 6.3.5 wakeup time from low-power mode the wakeup times given in the following table are measured with the msi or hsi16 rc oscillator. the clock source us ed to wake up the device d epends on the cu rrent op erating mode: ? sleep mode: the clock source is the clock that was set before entering sleep mode ? stop mode: the clock source is either the ms i oscillator in the range configured before entering stop mode, the hsi16 or hsi16/4. ? standby mode: the clock source is the msi oscillator running at 2.1 mhz all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . table 40. peripheral current consumption in stop and standby mode (1) symbol peripheral typical consumption, t a = 25 c unit v dd =1.8 v v dd =3.0 v i dd(pvd / bor) -0.71.2 a i refint --1.7 - lse low drive (2) 0.11 0,13 - lsi 0.27 0.31 -iwdg0.2 0.3 - lptim1, input 100 hz 0.01 0,01 - lptim1, input 1 mhz 11 12 - lpuart1 - 0,5 - rtc 0.16 0,3 1. lptim, lpuart peripherals can operate in stop mode but not in standby mode. 2. lse low drive consumption is the difference between an external clock on osc32_in and a quartz between osc32_in and osc32_out.- table 41. low-power mode wakeup timings symbol parameter conditions typ max unit t wusleep wakeup from sleep mode f hclk = 32 mhz 7 8 number of clock cycles t wusleep_ lp wakeup from low-power sleep mode, f hclk = 262 khz f hclk = 262 khz ? flash memory enabled 78 f hclk = 262 khz ? flash memory switched off 910 electrical characteristics stm32l071xx 74/136 docid027101 rev 3 t wustop wakeup from stop mode, regulator in run mode f hclk = f msi = 4.2 mhz 5.0 8 s f hclk = f hsi = 16 mhz 4.9 7 f hclk = f hsi /4 = 4 mhz 8.0 11 wakeup from stop mode, regulator in low- power mode f hclk = f msi = 4.2 mhz ? voltage range 1 5.0 8 f hclk = f msi = 4.2 mhz ? voltage range 2 5.0 8 f hclk = f msi = 4.2 mhz ? voltage range 3 5.0 8 f hclk = f msi = 2.1 mhz 7.3 13 f hclk = f msi = 1.05 mhz 13 23 f hclk = f msi = 524 khz 28 38 f hclk = f msi = 262 khz 51 65 f hclk = f msi = 131 khz 100 120 f hclk = msi = 65 khz 190 260 f hclk = f hsi = 16 mhz 4.9 7 f hclk = f hsi /4 = 4 mhz 8.0 11 wakeup from stop mode, regulator in low- power mode, code running from ram f hclk = f hsi = 16 mhz 4.9 7 f hclk = f hsi /4 = 4 mhz 7.9 10 f hclk = f msi = 4.2 mhz 4.7 8 t wustdby wakeup from standby mode ? fwu bit = 1 f hclk = msi = 2.1 mhz 65 130 wakeup from standby mode ? fwu bit = 0 f hclk = msi = 2.1 mhz 2.2 3 ms table 41. low-power mode wakeup timings (continued) symbol parameter conditions typ max unit docid027101 rev 3 75/136 stm32l071xx electrical characteristics 107 6.3.6 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio.the external clock signal has to re spect the i/o characteristics in section 6.3.12 . however, the recommended clock input waveform is shown in figure 21 . figure 21. high-speed external clock source ac timing diagram table 42. high-speed external user clock characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit f hse_ext user external clock source frequency css is on or pll is used 1832mhz css is off, pll not used 0832mhz v hseh osc_in input pin high level voltage - 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time 12 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 c in(hse) osc_in input capacitance - 2.6 - pf ducy (hse) duty cycle 45 - 55 % i l osc_in input leakage current v ss ?? v in ?? v dd --1a d l f 2 6 & b , 1 ( ; 7 ( 5 1 $ / 6 7 0 / [ [ & / 2 & . 6 2 8 5 & ( 9 + 6 ( + w i + 6 ( w : + 6 ( , / 7 + 6 ( w w u + 6 ( w : + 6 ( i + 6 ( b h [ w 9 + 6 ( / electrical characteristics stm32l071xx 76/136 docid027101 rev 3 low-speed external user clock generated from an external source the characteristics given in the following table result from tests performed using a low- speed external clock source, and under ambien t temperature and supply voltage conditions summarized in table 25 . figure 22. low-speed external clock source ac timing diagram table 43. low-speed external user clock characteristics (1) 1. guaranteed by design, not tested in production symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - 1 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t w(lse) osc32_in high or low time 465 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 10 c in(lse) osc32_in input capacitance - - 0.6 - pf ducy (lse) duty cycle - 45 - 55 % i l osc32_in input leakage current v ss ?? v in ?? v dd --1a d l f 2 6 & b , 1 ( ; 7 ( 5 1 $ / 6 7 0 / [ [ & / 2 & . 6 2 8 5 & ( 9 / 6 ( + w i / 6 ( w : / 6 ( , / 7 / 6 ( w w u / 6 ( w : / 6 ( i / 6 ( b h [ w 9 / 6 ( / docid027101 rev 3 77/136 stm32l071xx electrical characteristics 107 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 1 to 25 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 44 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 23 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? availabl e from the st website www.st.com . figure 23. hse oscilla tor circuit diagram table 44. hse oscillator characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit f osc_in oscillator frequency - 1 25 mhz r f feedback resistor - - 200 - k ? g m maximum critical crystal transconductance startup - - 700 a /v t su(hse) (2) 2. guaranteed by characterization results. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillat ion is reached. this value is measured for a standard crystal resonator and it can vary signif icantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms 2 6 & b 2 8 7 2 6 & b , 1 i + 6 ( w r f r u h & / & / 5 ) 6 7 0 5 h v r q d w r u & r q v x p s w l r q f r q w u r o j p 5 p & p / p & 2 5 h v r q d w r u d l e electrical characteristics stm32l071xx 78/136 docid027101 rev 3 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 45 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 24. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. table 45. lse oscillator characteristics (1) symbol parameter conditions (2) min (2) typ max unit f lse lse oscillator frequency - 32.768 - khz g m maximum critical crystal transconductance lsedrv[1:0]=00 lower driving capability --0.5 a/v lsedrv[1:0]= 01 medium low driving capability - - 0.75 lsedrv[1:0] = 10 medium high driving capability --1.7 lsedrv[1:0]=11 higher driving capability --2.7 t su(lse) (3) startup time v dd is stabilized - 2 - s 1. guaranteed by design. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. guaranteed by characterization results. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this val ue is measured for a standard crystal resonator and it can vary significantly with the crystal manufacture r. to increase speed, address a lower-dri ve quartz with a high- driver mode. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / docid027101 rev 3 79/136 stm32l071xx electrical characteristics 107 6.3.7 internal clock source characteristics the parameters given in table 46 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . high-speed internal 16 mhz (hsi16) rc oscillator figure 25. hsi16 minimum and maxi mum value versus temperature table 46. 16 mhz hsi16 oscillator characteristics symbol parameter conditions min typ max unit f hsi16 frequency v dd = 3.0 v - 16 - mhz trim (1)(2) 1. the trimming step differs depending on the trimming code. it is usually negativ e on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). hsi16 user- trimmed resolution trimming code is not a multiple of 16 - ?? 0.4 0.7 % trimming code is a multiple of 16 - - ?? 1.5 % acc hsi16 (2) 2. guaranteed by characterization results. accuracy of the factory-calibrated hsi16 oscillator v dda = 3.0 v, t a = 25 c -1 (3) 3. guaranteed by test in production. -1 (3) % v dda = 3.0 v, t a = 0 to 55 c -1.5 - 1.5 % v dda = 3.0 v, t a = -10 to 70 c -2 - 2 % v dda = 3.0 v, t a = -10 to 85 c -2.5 - 2 % v dda = 3.0 v, t a = -10 to 105 c -4 - 2 % v dda = 1.65 v to 3.6 v ? t a = ? 40 to 125 c -5.45 - 3.25 % t su(hsi16) (2) hsi16 oscillator startup time - - 3.7 6 s i dd(hsi16) (2) hsi16 oscillator power consumption - - 100 140 a 0 6 y 9 9 p l q 9 w \ s 9 p d [ 9 p d [ 9 p l q electrical characteristics stm32l071xx 80/136 docid027101 rev 3 low-speed internal (lsi) rc oscillator multi-speed internal (msi) rc oscillator table 47. lsi oscillator characteristics symbol parameter min typ max unit f lsi (1) 1. guaranteed by test in production. lsi frequency 26 38 56 khz d lsi (2) 2. this is a deviation for an individual part, once the init ial frequency has been measured. lsi oscillator frequency drift ? 0c ? t a ? 85c -10 - 4 % t su(lsi) (3) 3. guaranteed by design. lsi oscillator startup time - - 200 s i dd(lsi) (3) lsi oscillator power consumption - 400 510 na table 48. msi oscillator characteristics symbol parameter condition typ max unit f msi frequency after factory calibration, done at v dd = 3.3 v and t a = 25 c msi range 0 65.5 - khz msi range 1 131 - msi range 2 262 - msi range 3 524 - msi range 4 1.05 - mhz msi range 5 2.1 - msi range 6 4.2 - acc msi frequency error after factory calibration - ? 0.5 - % d temp(msi) (1) msi oscillator frequency drift ? 0 c ? t a ? 85 c - ? 3- % msi oscillator frequency drift ? v dd = 3.3 v, ? 40 c ? t a ? 110 c msi range 0 ? 8.9 +7.0 msi range 1 ? 7.1 +5.0 msi range 2 ? 6.4 +4.0 msi range 3 ? 6.2 +3.0 msi range 4 ? 5.2 +3.0 msi range 5 ? 4.8 +2.0 msi range 6 ? 4.7 +2.0 d volt(msi) (1) msi oscillator frequency drift ? 1.65 v ? v dd ? 3.6 v, t a = 25 c --2.5%/v docid027101 rev 3 81/136 stm32l071xx electrical characteristics 107 i dd(msi) (2) msi oscillator power consumption msi range 0 0.75 - a msi range 1 1 - msi range 2 1.5 - msi range 3 2.5 - msi range 4 4.5 - msi range 5 8 - msi range 6 15 - t su(msi) msi oscillator startup time msi range 0 30 - s msi range 1 20 - msi range 2 15 - msi range 3 10 - msi range 4 6 - msi range 5 5 - msi range 6, voltage range 1 and 2 3.5 - msi range 6, voltage range 3 5- t stab(msi) (2) msi oscillator stabilization time msi range 0 - 40 s msi range 1 - 20 msi range 2 - 10 msi range 3 - 4 msi range 4 - 2.5 msi range 5 - 2 msi range 6, voltage range 1 and 2 -2 msi range 3, voltage range 3 -3 f over(msi) msi oscillator frequency overshoot any range to range 5 -4 mhz any range to range 6 -6 1. this is a deviation for an individual part, once the init ial frequency has been measured. 2. guaranteed by characterization results. table 48. msi oscillator characteristics (continued) symbol parameter condition typ max unit electrical characteristics stm32l071xx 82/136 docid027101 rev 3 6.3.8 pll characteristics the parameters given in table 49 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . 6.3.9 memory characteristics ram memory flash memory and data eeprom table 49. pll characteristics symbol parameter value unit min typ max (1) 1. guaranteed by characterization results. f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 2- 24mhz pll input clock duty cycle 45 - 55 % f pll_out pll output clock 2 - 32 mhz t lock pll input = 16 mhz pll vco = 96 mhz - 115 160 s jitter cycle-to-cycle jitter - ? 600 ps i dda (pll) current consumption on v dda - 220 450 a i dd (pll) current consumption on v dd - 120 150 table 50. ram and hardware registers symbol parameter cond itions min typ max unit vrm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware registers (only in stop mode). stop mode (or reset) 1.65 - - v table 51. flash memo ry and data eeprom characteristics symbol parameter conditions min typ max (1) unit v dd operating voltage read / write / erase -1.65-3.6v t prog programming time for word or half-page erasing - 3.28 3.94 ms programming - 3.28 3.94 docid027101 rev 3 83/136 stm32l071xx electrical characteristics 107 6.3.10 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. i dd average current during the whole programming / erase operation t a ??? 25 c, v dd = 3.6 v - 500 700 a maximum current (peak) during the whole programming / erase operation -1.52.5ma 1. guaranteed by design. table 52. flash memory and data eeprom endurance and retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization results. n cyc (2) cycling (erase / write) ? program memory t a ??? -40c to 105 c 10 kcycles cycling (erase / write) ? eeprom data memory 100 cycling (erase / write) ? program memory t a ??? -40c to 125 c 0.2 cycling (erase / write) ? eeprom data memory 2 t ret (2) 2. characterization is done according to jedec jesd22-a117. data retention (program memory) after 10 kcycles at t a = 85 c t ret = +85 c 30 years data retention (eeprom data memory) after 100 kcycles at t a = 85 c 30 data retention (program memory) after 10 kcycles at t a = 105 c t ret = +105 c 10 data retention (eeprom data memory) after 100 kcycles at t a = 105 c data retention (program memory) after 200 cycles at t a = 125 c t ret = +125 c data retention (eeprom data memory) after 2 kcycles at t a = 125 c table 51. flash memo ry and data eeprom characteristics symbol parameter conditions min typ max (1) unit electrical characteristics stm32l071xx 84/136 docid027101 rev 3 functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 53 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 53. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp100, t a ?? +25 c, ? f hclk ?? 32 mhz ? conforms to iec 61000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp100, t a ?? +25 c, ? f hclk ?? 32 mhz ? conforms to iec 61000-4-4 4a docid027101 rev 3 85/136 stm32l071xx electrical characteristics 107 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 54. emi characteristics symbol parameter conditions monitored frequency band max vs. frequency range at 32 mhz unit s emi peak level v dd ?? 3.6 v, t a ?? 25 c, ? lqfp100 package ? compliant with iec 61967-2 0.1 to 30 mhz -7 dbv 30 to 130 mhz 14 130 mhz to 1 ghz 9 emi level 2 - electrical characteristics stm32l071xx 86/136 docid027101 rev 3 6.3.11 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. table 55. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to ansi/jedec js-001 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to ansi/esd stm5.3.1. c4 500 table 56. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +125 c conforming to jesd78a ii level a docid027101 rev 3 87/136 stm32l071xx electrical characteristics 107 6.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or ot her functional failure (for ex ample reset occurrence oscillator frequency deviation). the test results are given in the table 57 . table 57. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on pa0, pa4, pa5, pc15, ph0 and ph1 -5 0 injected current on any other ft, ftf pins -5 (1) 1. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. na injected current on any other pins -5 (1) +5 electrical characteristics stm32l071xx 88/136 docid027101 rev 3 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 58 are derived from tests performed under the conditions summarized in table 25 . all i/os are cmos and ttl compliant. table 58. i/o static characteristics symbol parameter c onditions min typ max unit v il input low level voltage tc, ft, ftf, rst i/os - - 0.3v dd v boot0 pin - - 0.14v dd (1) v ih input high level voltage all i/os 0.7 v dd -- v hys i/o schmitt trigger voltage hysteresis (2) standard i/os - 10% v dd (3) - boot0 pin - 0.01 - i lkg input leakage current (4) v ss ?? v in ?? v dd all i/os except for pa11, pa12, boot0 and ftf i/os --50 na v ss ?? v in ?? v dd , pa11 and pa12 i/os - - -50/+250 v ss ?? v in ?? v dd ftf i/os - - 100 v dd ?? v in ?? 5 v all i/os except for pa11, pa12, boot0 and ftf i/os - - 200 na v dd ?? v in ?? 5 v ftf i/os - - 500 v dd ?? v in ?? 5 v pa11, pa12 and boot0 --10a r pu weak pull-up equivalent resistor (5) v in ?? v ss 30 45 60 k ? r pd weak pull-down equivalent resistor (5) v in ?? v dd 30 45 60 k ? c io i/o pin capacitance - - 5 - pf 1. g uaranteed by characterization. 2. hysteresis voltage between schmi tt trigger switching levels. guar anteed by characterization results. 3. with a minimum of 200 mv. guaranteed by characterization results. 4. the max. value may be exceeded if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistors are designed with a true resi stance in series with a sw itchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order). docid027101 rev 3 89/136 stm32l071xx electrical characteristics 107 figure 26. v ih /v il versus vdd (cmos i/os) figure 27. v ih /v il versus vdd (ttl i/os) output driving current the gpios (general purpose input/outputs) can si nk or source up to 8 ma, and sink or source up to 15 ma with the non-standard v ol /v oh specifications given in table 59 . in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd( ) (see table 23 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss( ) (see table 23 ). 0 6 y 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' d o o s l q v h [ f h s w % 2 2 7 3 & 3 + 9 , + p l q 9 ' ' i r u % 2 2 7 3 & 3 + , q s x w u d q j h q r w j x d u d q w h h g 0 6 y 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 , q s x w u d q j h q r w j x d u d q w h h g 9 , + p l q 9 ' ' d o o s l q v h [ f h s w % 2 2 7 3 & 3 + 9 , + p l q 9 ' ' i r u % 2 2 7 3 & 3 + electrical characteristics stm32l071xx 90/136 docid027101 rev 3 output voltage levels unless otherwise specified, the parameters given in table 59 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . all i/os are cmos and ttl compliant. table 59. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always respect the absolute maximum rating specified in table 23 . the sum of the currents sunk by all the i/os (i/o ports and control pins) must always be respected and must not exceed i io(pin) . output low level voltage for an i/o pin cmos port (2) , i io = +8 ma 2.7 v ??? v dd ?? 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 23 . the sum of the currents sourced by all the i/o s (i/o ports and control pins) must always be respected and must not exceed i io(pin) . output high level voltage for an i/o pin v dd -0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) , i io =+ 8 ma 2.7 v ?? v dd ?? 3.6 v -0.4 v oh (3)(4) 4. guaranteed by characterization results. output high level voltage for an i/o pin ttl port (2) , i io = -6 ma 2.7 v ?? v dd ?? 3.6 v 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +15 ma 2.7 v ?? v dd ?? 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin i io = -15 ma 2.7 v ?? v dd ?? 3.6 v v dd -1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +4 ma 1.65 v ?? v dd < 3.6 v -0.45 v oh (3)(4) output high level voltage for an i/o pin i io = -4 ma 1.65 v ?? v dd ?? 3.6 v v dd -0.45 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = 20 ma 2.7 v ?? v dd ?? 3.6 v -0.4 i io = 10 ma 1.65 v ?? v dd ?? 3.6 v -0.4 docid027101 rev 3 91/136 stm32l071xx electrical characteristics 107 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 28 and table 60 , respectively. unless otherwise specified, the parameters given in table 60 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . table 60. i/o ac characteristics (1) ospeedrx[1:0] bit value (1) symbol parameter conditions min max (2) unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 400 khz c l = 50 pf, v dd = 1.65 v to 2.7 v - 100 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 125 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 320 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 2 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 0.6 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 65 10 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 10 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 2 t f(io)out t r(io)out output rise and fall time c l = 50 pf, v dd = 2.7 v to 3.6 v - 13 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 28 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd = 2.7 v to 3.6 v - 35 mhz c l = 50 pf, v dd = 1.65 v to 2.7 v - 10 t f(io)out t r(io)out output rise and fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 6 ns c l = 50 pf, v dd = 1.65 v to 2.7 v - 17 fm+ configuration (4) f max(io)out maximum frequency (3) c l = 50 pf, v dd = 2.5 v to 3.6 v -1mhz t f(io)out output fall time - 10 ns t r(io)out output rise time - 30 f max(io)out maximum frequency (3) c l = 50 pf, v dd = 1.65 v to 3.6 v -350khz t f(io)out output fall time - 15 ns t r(io)out output rise time - 60 -t extipw pulse width of external signals detected by the exti controller -8-ns 1. the i/o speed is configured using the ospee drx[1:0] bits. refer to the line reference manual for a description of gpio port configuration register. 2. guaranteed by design. 3. the maximum frequency is defined in figure 28 . 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the line reference manual for a detailed description of fm+ i/o configuration. electrical characteristics stm32l071xx 92/136 docid027101 rev 3 figure 28. i/o ac charac teristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu , except when it is internally driven low (see table 61 ). unless otherwise specified, the parameters given in table 61 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 25 . d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w table 61. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design. nrst input low level voltage - v ss -0.8 v v ih(nrst) (1) nrst input high level voltage - 1.4 - v dd v ol(nrst) (1) nrst output low level voltage i ol = 2 ma 2.7 v < v dd < 3.6 v -- 0.4 i ol = 1.5 ma 1.65 v < v dd < 2.7 v -- v hys(nrst) (1) nrst schmitt trigger voltage hysteresis --10%v dd (2) 2. 200 mv minimum value -mv r pu weak pull-up equivalent resistor (3) 3. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is around 10%. v in ?? v ss 30 45 60 k ? v f(nrst) (1) nrst input filtered pulse - - - 50 ns v nf(nrst) (1) nrst input not filtered pulse - 350 - - ns docid027101 rev 3 93/136 stm32l071xx electrical characteristics 107 figure 29. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 61 . otherwise the reset will not be taken into account by the device. 6.3.15 12-bit adc characteristics unless otherwise specified, the parameters given in table 62 are derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions summarized in table 25: general operating conditions . note: it is recommended to perform a calibration after each power-up. d l f 6 7 0 / [ [ 5 3 8 1 5 6 7 9 ' ' ) l o w h u , q w h u q d o u h v h w ? ) ( [ w h u q d o u h v h w f l u f x l w table 62. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on fast channel 1.65 - 3.6 v standard channel 1.75 (1) -3.6 v ref+ positive reference voltage - 1.65 v dda v v ref- negative reference voltage - - 0 - i dda (adc) current consumption of the adc on v dda and v ref+ 1.14 msps - 200 - a 10 ksps - 40 - current consumption of the adc on v dd (2) 1.14 msps - 70 - 10 ksps - 1 - f adc adc clock frequency voltage scaling range 1 0.14 - 16 mhz voltage scaling range 2 0.14 - 8 voltage scaling range 3 0.14 - 4 f s (3) sampling rate 12-bit resolution 0.01 - 1.14 mhz f trig (3) external trigger frequency f adc = 16 mhz, 12-bit resolution - - 941 khz ---171/f adc v ain conversion voltage range - 0 - v ref+ v r ain (3) external input impedance see equation 1 and table 63 for details --50k ? r adc (3)(4) sampling switch resistance - - - 1 k ? electrical characteristics stm32l071xx 94/136 docid027101 rev 3 c adc (3) internal sample and hold capacitor ---8pf t cal (3)(5) calibration time f adc = 16 mhz 5.2 s -831/f adc w latency (6) adc_dr register write latency adc clock = hsi16 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles - adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (3) trigger conversion latency f adc = f pclk /2 = 16 mhz 0.266 s f adc = f pclk /2 8.5 1/f pclk f adc = f pclk /4 = 8 mhz 0.516 s f adc = f pclk /4 16.5 1/f pclk f adc = f hsi16 = 16 mhz 0.252 - 0.260 s jitter adc adc jitter on trigger conversion f adc = f hsi16 -1-1/f hsi16 t s (3) sampling time f adc = 16 mhz 0.093 - 10.03 s - 1.5 - 160.5 1/f adc t up_ldo (3)(5) internal ldo power-up time - - - 10 s t stab (3)(5) adc stabilization time - 14 1/f adc t conv (3) total conversion time (including sampling time) f adc = 16 mhz, 12-bit resolution 0.875 - 10.81 s 12-bit resolution 14 to 173 (t s for sampling +12.5 for successive approximation) 1/f adc 1. v dda minimum value can be decreased in spec ific temperature conditions. refer to table 63: rain max for fadc = 16 mhz . 2. a current consumption proportional to the apb clock frequency has to be added (see table 39: peripheral current consumption in run or sleep mode ). 3. guaranteed by design. 4. standard channels have an extra protection resi stance which depends on supply voltage. refer to table 63: rain max for fadc = 16 mhz . 5. this parameter only includes the adc timing. it does not take into account register access latency. 6. this parameter specifies the latency to tr ansfer the conversion result into the adc_dr register. eoc bit is set to indicate t he conversion is complete and has the same latency. table 62. adc characteristics (continued) symbol parameter conditions min typ max unit docid027101 rev 3 95/136 stm32l071xx electrical characteristics 107 equation 1: r ain max formula the simplified formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). r ain t s f adc c adc 2 n2 + ?? ln ? ? ------------------------------------------------------------- - r adc ? ? table 63. r ain max for f adc = 16 mhz (1) t s (cycles) t s (s) r ain max for fast channels (k ? ) r ain max for standard channels (k ? ) v dd > 2.7 v v dd > 2.4 v v dd > 2.0 v v dd > 1.8 v v dd > 1.75 v v dd > 1.65 v and t a > ? 10 c v dd > 1.65 v and t a > 25 c 1.5 0.09 0.5 < 0.1 na na na na na na 3.5 0.22 1 0.2 < 0.1 na na na na na 7.5 0.47 2.5 1.7 1.5 < 0.1 na na na na 12.5 0.78 4 3.2 3 1 na na na na 19.5 1.22 6.5 5.7 5.5 3.5 na na na < 0.1 39.5 2.47 13 12.2 12 10 na na na 5 79.5 4.97 27 26.2 26 24 < 0.1 na na 19 160.5 10.03 50 49.2 49 47 32 < 0.1 < 0.1 42 1. guaranteed by design. table 64. adc accuracy (1)(2)(3) symbol parameter conditions min typ max unit et total unadjusted error 1.65 v < v dda = v ref+ < 3.6 v, range 1/2/3 -2 4 lsb eo offset error - 1 2.5 eg gain error - 1 2 el integral linearity error - 1.5 2.5 ed differential linearity error - 1 1.5 enob effective number of bits 10.2 11 bits effective number of bits (16-bit mode oversampling with ratio =256) (4) 11.3 12.1 - sinad signal-to-noise distortion 63 69 - db snr signal-to-noise ratio 63 69 - signal-to-noise ratio (16-bit mode oversampling with ratio =256) (4) 70 76 - thd total harmonic distortion - -85 -73 electrical characteristics stm32l071xx 96/136 docid027101 rev 3 figure 30. adc accuracy characteristics et total unadjusted error 1.65 v < v ref+ electrical characteristics stm32l071xx 98/136 docid027101 rev 3 figure 33. power supply and reference decoupling (v ref+ connected to v dda ) 6.3.16 temperature sensor characteristics 0 6 9 6 2 % & 6 $ $ ! 6 7 0 / [ [ ? & n & 6 2 % & n 6 3 3 ! table 65. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3 v 0x1ff8 007a - 0x1ff8 007b ts_cal2 ts adc raw data acquired at temperature of 130 c, v dda = 3 v 0x1ff8 007e - 0x1ff8 007f table 66. temperature sensor characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by characterization results. v sense linearity with temperature - ? 1 ? 2c avg_slope (1) average slope 1.48 1.61 1.75 mv/c v 130 voltage at 130c 5c (2) 2. measured at v dd = 3 v 10 mv. v130 adc conversion result is stored in the ts_cal2 byte. 640 670 700 mv i dda (temp) (3) current consumption - 3.4 6 a t start (3) 3. guaranteed by design. startup time - - 10 s t s_temp (4)(3) 4. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 10 - - docid027101 rev 3 99/136 stm32l071xx electrical characteristics 107 6.3.17 comparators table 67. comparator 1 characteristics symbol parameter conditions min (1) typ max (1) unit v dda analog supply voltage - 1.65 3.6 v r 400k r 400k value - - 400 - k ? r 10k r 10k value - - 10 - v in comparator 1 input voltage range -0.6-v dda v t start comparator startup time - - 7 10 s td propagation delay (2) --310 voffset comparator offset - - ? 3 ? 10 mv d voffset /dt comparator offset variation in worst voltage stress conditions v dda ?? 3.6 v, v in+ ?? 0 v, v in- ?? v refint , t a = 25 ? c 0 1.5 10 mv/1000 h i comp1 current consumption (3) - - 160 260 na 1. guaranteed by characterization. 2. the delay is characteri zed for 100 mv input step with 10 mv overdrive on the inverting input, the non-inverting input set to the reference. 3. comparator consumption only. inte rnal reference voltage not included. table 68. comparator 2 characteristics symbol parameter conditions min typ max (1) unit v dda analog supply voltage - 1.65 - 3.6 v v in comparator 2 input voltage range - 0 - v dda v t start comparator startup time fast mode - 15 20 s slow mode - 20 25 t d slow propagation delay (2) in slow mode 1.65 v ? v dda ? 2.7 v - 1.8 3.5 2.7 v ? v dda ? 3.6 v - 2.5 6 t d fast propagation delay (2) in fast mode 1.65 v ? v dda ? 2.7 v - 0.8 2 2.7 v ? v dda ? 3.6 v - 1.2 4 v offset comparator offset error - ? 4 ? 20 mv dthreshold/ dt threshold voltage temperature coefficient v dda ?? 3.3v, t a = 0 to 50 ? c, ? v- = v refint , ? 3/4 v refint , ? 1/2 v refint , ? 1/4 v refint . -15 30 ppm /c i comp2 current consumption (3) fast mode - 3.5 5 a slow mode - 0.5 2 1. guaranteed by characterization results. 2. the delay is characterized for 100 mv input step with 10 mv ov erdrive on the inverting input, the non-inverting input set to the reference. 3. comparator consumption only. internal reference vo ltage (required for comparator operation) is not included. electrical characteristics stm32l071xx 100/136 docid027101 rev 3 6.3.18 timer characteristics tim timer characteristics the parameters given in the table 69 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 6.3.19 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm) : with a bit rate up to 100 kbit/s ? fast-mode (fm) : with a bit rate up to 400 kbit/s ? fast-mode plus (fm+) : with a bit rate up to 1 mbit/s. the i 2 c timing requirements are guaranteed by design when the i 2 c peripheral is properly configured (refer to the reference manual for details). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not "true" open-drain. when configured as open-drain, the pmos c onnected between the i/ o pin and vddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement (refer to section 6.3.13: i/o port characteristics for the i2c i/os characteristics). all i 2 c sda and scl i/os embed an analog filter (see table 70 for the analog filter characteristics). table 69. timx characteristics (1) symbol parameter conditions min max unit t res(tim) timer resolution time 1-t timxclk f timxclk = 32 mhz 31.25 - ns f ext timer external clock frequency on ch1 to ch4 0f timxclk /2 mhz f timxclk = 32 mhz 0 16 mhz res tim timer resolution - 16 bit t counter 16-bit counter clock period when internal clock is selected (timer?s prescaler disabled) - 1 65536 t timxclk f timxclk = 32 mhz 0.0312 2048 s t max_count maximum possible count - - 65536 65536 t timxclk f timxclk = 32 mhz - 134.2 s 1. timx is used as a general term to refer to the tim2, tim6, tim21, and tim22 timers. docid027101 rev 3 101/136 stm32l071xx electrical characteristics 107 the analog spike filter is compliant with i 2 c timings requirements only for the following voltage ranges: ? fast mode plus: 2.7 v ? ? v dd ?? 3.6 v and voltage scaling range 1 ? fast mode: ?2 v ? v dd ? 3.6 v and voltage scaling range 1 or range 2. ?v dd < 2 v, voltage scaling range 1 or range 2, c load < 200 pf. in other ranges, the analog filter should be di sabled. the digital filter can be used instead. note: in standard mode, no spike filter is required. usart/lpuart characteristics the parameters given in the following table are guaranteed by design. table 70. i2c analog filter characteristics (1) 1. guaranteed by characterization results. symbol parameter conditions min max unit t af maximum pulse width of spikes that are suppressed by the analog filter range 1 50 (2) 2. spikes with widths below t af(min) are filtered. 100 (3) 3. spikes with widths above t af(max) are not filtered ns range 2 - range 3 - table 71. usart/lpuart characteristics symbol parameter conditions typ max unit t wuusart wakeup time needed to calculate the maximum usart/lpuart baudrate allowing to wake up from stop mode stop mode with main regulator in run mode, range 2 or 3 -8.7 s stop mode with main regulator in run mode, range 1 -8.1 stop mode with main regulator in low-power mode, range 2 or 3 -12 stop mode with main regulator in low-power mode, range 1 -11.4 electrical characteristics stm32l071xx 102/136 docid027101 rev 3 spi characteristics unless otherwise specified, th e parameters given in the following tables are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions su mmarized in table 25 . refer to section 6.3.12: i/o current injection char acteristics for more details on the input/output alternate function char acteristics (nss, sck, mosi, miso). table 72. spi characteristics in voltage range 1 (1) 1. guaranteed by characterization results. symbol parameter cond itions min typ max unit f sck 1/t c(sck) spi clock frequency master mode -- 16 mhz slave mode receiver 16 slave mode transmitter 1.71 docid027101 rev 3 105/136 stm32l071xx electrical characteristics 107 figure 35. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. figure 36. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd. d l 6 & . , q s x w & 3 + $ 0 2 6 , , 1 3 8 7 0 , 6 2 2 8 7 3 8 7 & 3 + $ 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % , 1 / 6 % 2 8 7 & 3 2 / & 3 2 / % , 7 , 1 w 6 8 1 6 6 w f 6 & . w k 1 6 6 w d 6 2 w z 6 & . + w z 6 & . / w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w v x 6 , w k 6 , 1 6 6 l q s x w d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics stm32l071xx 106/136 docid027101 rev 3 i2s characteristics note: refer to the i2s section of the product refe rence manual for more details about the sampling frequency (fs), f mck , f ck and d ck values. these values reflect only the digital peripheral behavior, source clock precision might slig htly change them. dck depends mainly on the odd bit value, digital contribution leads to a min of (i2sdiv/(2*i2sdiv+odd) and a max of (i2sdiv+odd)/(2*i2sdiv+odd). fs max is supported for each mode/condition. table 75. i2s characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256 x 8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode - 15 ns t h(ws) ws hold time master mode 11 - t su(ws) ws setup time slave mode 6 - t h(ws) ws hold time slave mode 2 - t su(sd_mr) data input setup time master receiver 0 - t su(sd_sr) slave receiver 6.5 - t h(sd_mr) data input hold time master receiver 18 - t h(sd_sr) slave receiver 15.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 77 t v(sd_mt) master transmitter (after enable edge) - 8 t h(sd_st) data output hold time slave transmitter (after enable edge) 18 - t h(sd_mt) master transmitter (after enable edge) 1.5 - 1. guaranteed by characterization results. 2. 256xfs maximum value is equal to the maximum clock frequency. docid027101 rev 3 107/136 stm32l071xx electrical characteristics 107 figure 37. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 38. i 2 s master timing diagram (philips protocol) (1) 1. guaranteed by characterization results. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t package information stm32l071xx 108/136 docid027101 rev 3 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at www.st.com . ecopack ? is an st trademark. 7.1 lqfp100 package information figure 39. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 1. drawing is not to scale. dimensions are in millimeters. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! docid027101 rev 3 109/136 stm32l071xx package information 133 table 76. lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0. 6220 0.6299 0.6378 d1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0. 6220 0.6299 0.6378 e1 13.800 14.000 14.200 0. 5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 package information stm32l071xx 110/136 docid027101 rev 3 figure 40. lqfp100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. device marking for lqfp100 the following figure gives an example of topsid e marking versus pin 1 position identifier location. figure 41. lqfp100 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. a i c 0 6 y 9 6 7 0 / 9 = 7 5 : : 5 h y l v l r q f r g h 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h 3 l q l q g h q w l i l h u < docid027101 rev 3 111/136 stm32l071xx package information 133 7.2 ufbga100 package information figure 42. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline 1. drawing is not to scale. table 77. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 0.600 - - 0.0236 a1 - - 0.110 - - 0.0043 a2 - 0.450 - - 0.0177 - a3 - 0.130 - - 0.0051 0.0094 a4 - 0.320 - - 0.0126 - b 0.240 0.290 0.340 0.0094 0.0114 0.0134 d 6.850 7.000 7.150 0.2697 0.2756 0.2815 d1 - 5.500 - - 0.2165 - e 6.850 7.000 7.150 0.2697 0.2756 0.2815 e1 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - z - 0.750 - - 0.0295 - $ & b 0 ( b 9 6 h d w l q j s o d q h $ h = = ' 0 ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : $ e d o o l g h q w l i l h u h $ $ < ; = g g g = ' ( h h h = < ; i i i ? ? 0 0 = $ $ $ e d o o l q g h [ d u h d package information stm32l071xx 112/136 docid027101 rev 3 figure 43. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 78. ufbga100 recommended pcb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 dpad 0.280 mm dsm 0.370 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.280 mm stencil thickness between 0.100 mm and 0.125 mm table 77. ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. $ & b ) 3 b 9 ' s d g ' v p docid027101 rev 3 113/136 stm32l071xx package information 133 7.3 lqfp64 package information figure 44. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 1. drawing is not to scale. table 79. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d - 12.000 - - 0.4724 - d1 - 10.000 - - 0.3937 - d3 - 7.500 - - 0.2953 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p package information stm32l071xx 114/136 docid027101 rev 3 figure 45. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - k 03.57 03.57 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 79. lqfp64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c docid027101 rev 3 115/136 stm32l071xx package information 133 device marking for lqfp64 the following figure gives an example of topsid e marking versus pin 1 position identifier location. figure 46. lqfp64 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 6 7 0 / 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : 3 l q l q g h q w l i l h u 5 % 7 5 package information stm32l071xx 116/136 docid027101 rev 3 7.4 tfbga64 package information figure 47. tfbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline 1. drawing is not to scale. table 80. tfbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.200 - - 0.0472 a1 0.150 - - 0.0059 - - a2 - 0.200 - - 0.0079 - a4 - - 0.600 - - 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 d 4.850 5.000 5.150 0.1909 0.1969 0.2028 d1 - 3.500 - - 0.1378 - e 4.850 5.000 5.150 0.1909 0.1969 0.2028 e1 - 3.500 - - 0.1378 - 5 b 0 ( b 9 6 h d w l q j s o d q h $ h ) ) ' + ? e e d o o v $ ( 7 2 3 9 , ( : % 2 7 7 2 0 9 , ( : h $ % $ & g g g & ' ( h h h & % $ i i i ? ? 0 0 & $ $ $ e d o o l g h q w l i l h u $ e d o o l q g h [ d u h d 6 , ' ( 9 , ( : docid027101 rev 3 117/136 stm32l071xx package information 133 figure 48. tfbga64 ? 64-ball, 5 x 5 mm, 0. 5 mm pitch, thin profile fine pitch ball ,grid array recommended footprint note: non solder mask defined (nsmd) pads are recommended. 4 to 6 mils solder paste screen printing process. e - 0.500 - - 0.0197 - f - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. table 81. tfbga64 recommended pcb design rules (0.5 mm pitch bga) dimension recommended values pitch 0.5 dpad 0.27 mm dsm 0.35 mm typ. (depends on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter. table 80. tfbga64 ? 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 0 6 9 ' v p ' s d g package information stm32l071xx 118/136 docid027101 rev 3 device marking for tfbga64 the following figure gives an example of topside marking versus ball a 1 position identifier location. figure 49. tfbga64 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. / 5 = + 5 < : : 0 6 y 9 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < h d u z h h n % d o o $ 5 h y l v l r q f r g h docid027101 rev 3 119/136 stm32l071xx package information 133 7.5 wlcsp49 pac kage information figure 50. wlcsp49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. % r w w r p y l h z % x p s v l g h 6 l g h y l h z ) u r q w y l h z 7 r s y l h z : d i h u e d f n v l g h $ e d o o o r f d w l r q h ) * h h h ( ' $ $ ' h w d l o $ $ e e e = ' h w d l o $ u r w d w h g 6 h d w l q j s o d q h 1 r w h 1 r w h % x p s [ h h h = 2 u l h q w d w l r q u h i h u h q f h $ [ ' ( $ $ e $ b 0 ( b 9 $ e d d d f f f g g g = = ; < = package information stm32l071xx 120/136 docid027101 rev 3 figure 51. wlcsp49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale recommended footprint table 82. wlcsp49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 (2) 2. back side coating - 0.025 - - 0.0010 - b (3) 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 3.259 3.294 3.329 0.1283 0.1297 0.1311 e 3.223 3.258 3.293 0.1269 0.1283 0.1296 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - f - 0.447 - - 0.0176 - g - 0.429 - - 0.0169 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 0 6 9 ' v p ' s d g docid027101 rev 3 121/136 stm32l071xx package information 133 device marking for wlcsp49 the following figure gives an example of topside marking versus ball a 1 position identifier location. figure 52. wlcsp49 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 83. wlcsp49 recommended pcb design rules (0.4 mm pitch) dimension recommended values pitch 0.4 dpad 260 m max. (circular) 220 m recommended dsm 300 m min. (for 260 m diameter pad) pcb pad design non-solder mask defined via underbump allowed. 0 6 y 9 / & = < : : 3 u r g x f w l g h q w l i l f d w l r q % d o o l q g h q w l i l h u ' d w h f r g h 5 h y l v l r q f r g h 5 package information stm32l071xx 122/136 docid027101 rev 3 7.6 lqfp48 package information figure 53. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + docid027101 rev 3 123/136 stm32l071xx package information 133 table 84. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 package information stm32l071xx 124/136 docid027101 rev 3 figure 54. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. device marking for lqfp48 the following figure gives an example of topsid e marking versus pin 1 position identifier location. figure 55. lqfp48 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. a i d 6 7 0 / & = 7 0 6 y 9 3 l q l q g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : 5 h y l v l r q f r g h 5 docid027101 rev 3 125/136 stm32l071xx package information 133 7.7 lqfp32 package information figure 56. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e package information stm32l071xx 126/136 docid027101 rev 3 figure 57. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint 1. dimensions are expr essed in millimeters. table 85. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.100 - - 0.0039 6 ? & 0 ? 6 docid027101 rev 3 127/136 stm32l071xx package information 133 device marking for lqfp32 the following figure gives an example of topsid e marking versus pin 1 position identifier location. figure 58. lqfp32 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. . = 7 5 < : : 0 6 y 9 3 l q l q g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h 6 7 0 / ' d w h f r g h package information stm32l071xx 128/136 docid027101 rev 3 7.8 ufqfpn32 package information figure 59. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline 1. drawing is not to scale. ! " ? - % ? 6 3 , 1 , g h q w l i l h u 6 ( $ 7 , 1 * 3 / $ 1 ( & & g g g $ $ $ h e ' e ( / h ( ( ' / ' docid027101 rev 3 129/136 stm32l071xx package information 133 figure 60. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat recommended footprint 1. dimensions are expr essed in millimeters. table 86. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d1 3.400 3.500 3.600 0.1339 0.1378 0.1417 d2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e1 3.400 3.500 3.600 0.1339 0.1378 0.1417 e2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 $ % b ) 3 b 9 package information stm32l071xx 130/136 docid027101 rev 3 device marking for ufqfpn32 the following figure gives an example of topsid e marking versus pin 1 position identifier location. figure 61. ufqfpn32 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. / . = 0 6 y 9 3 l q l q g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : 5 h y l v l r q f r g h 5 docid027101 rev 3 131/136 stm32l071xx package information 133 7.9 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max ? ja ) where: ? t a max is the maximum ambient temperature in ? c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. table 87. thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient ufqfpn32 - 5 x 5 mm / 0.5 mm pitch 36 c/w thermal resistance junction-ambient lqfp32 - 7 x 7 mm / 0.8 mm pitch 60 thermal resistance junction-ambient lqfp48 - 7 x 7 mm / 0.5 mm pitch 54 thermal resistance junction-ambient wlcsp49 - 0.4 mm pitch 48 thermal resistance junction-ambient tfbga64 - 5 x 5 mm / 0.5 mm pitch 64 thermal resistance junction-ambient lqfp64 - 10 x 10 mm / 0.5 mm pitch 46 thermal resistance junction-ambient ? lqfp100 - 14 x 14 mm / 0.5 mm pitch 41 thermal resistance junction-ambient ? ufbga100 - 7 x 7 mm / 0.5 mm pitch 57 package information stm32l071xx 132/136 docid027101 rev 3 figure 62. thermal resistance 7.9.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 0 6 y 9 7 h p s h u d w x u h ? & 3 ' p : ? ? ? ?? ? ?? e ?? ? ? ?? > y & we > y & we? d & ' e > y & w h & ' t > ^ we? h y & e?? > y & w e?? docid027101 rev 3 133/136 stm32l071xx part numbering 133 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 88. stm32l071xx ordering information scheme example: stm32 l 071 r 8 t 6 d tr device family stm32 = arm-based 32-bit microcontroller product type l = low power device subfamily 071 = access line pin count k = 32 pins c = 48/49 pins r = 64 pins v = 100 pins flash memory size 8 = 64 kbytes b = 128 kbytes z = 192 kbytes package t = lqfp h = tfbga i = ufbga u = ufqfpn y = wlcsp pins temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c 3 = industrial temperature range, ?40 to 125 c options no character = v dd range: 1.8 to 3.6 v and bor enabled d = v dd range: 1.65 to 3.6 v and bor disabled packing tr = tape and reel no character = tray or tube revision history stm32l071xx 134/136 docid027101 rev 3 9 revision history table 89. document revision history date revision changes 02-sep-2015 1 initial release 26-oct-2015 2 changed confidentiality level to public. updated datasheet status to ?production data?. modified ultra-low-power platfo rm features on cover page. in table 15: stm32l07 1xxx pin definition : ? changed pin name to vddio2 for the following pins: ufqfpn32 pin 24, lqfp48 pin 36, lqfp64 pin 48, ufbga64 pin e5, wlcsp49 pin a1, lqfp100 pin 75 and ufbga100 pin g11. ? added note related to ufqfpn32. in section 6: electrical characteristics , updated notes related to values guaranteed by characterization. updated | ? v ss | definition to include v ref- in table 22: voltage characteristics . updated f trig and v ain maximum value, added v ref+ and v ref- in table 62: adc characteristics . added section : device marking for lqfp100 . updated figure 42: ufbga100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline and table 76: lqpf100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data . added section : device marking for lqfp100 , section : device marking for lqfp64 , section : device ma rking for tfbga64 and section : device marking for wlcsp49 . updated figure 55: lqfp48 marking example (package top view) . docid027101 rev 3 135/136 stm32l071xx revision history 135 22-mar-2016 3 updated number of spis on cover page and in table 2: ultra-low- power stm32l071xx device features and peripheral counts . changed minimum comparator supply voltage to 1.65 v on cover page. added number of fast and standard channels in section 3.11: analog-to-digital converter (adc) . updated section 3.15.2: universal synchronous/asynchronous receiver transmitter (usart) and section 3.15.4: serial peripheral interface (spi)/inter-integrated sound (i2s) to mention the fact that usarts with syn chronous mode feature can be used as spi master interfaces. added baudrate allowing to wake up the mcu from stop mode in section 3.15.2: universal synchronous/asynchronous receiver transmitter (usart) and section 3.15.3: low-power universal asynchronous receiver transmitter (lpuart) . changed v dda minimum value to 1.65 v in table 25: general operating conditions . section 6.3.15: 12-bit adc characteristics : ? table 62: adc characteristics : distinction made between v dda for fast and standard channels; added note 1. added note 4. related to r adc . updated f trig . and v ain maximum value. updated t s and t conv . added v ref+ . ? updated equation 1 description. ? updated table 63: rain max for fadc = 16 mhz for f adc = 16 mhz and distinction made between fast and standard channels. added table 71: usart/lpuart characteristics . table 89. document revision history date revision changes stm32l071xx 136/136 docid027101 rev 3 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
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